Start changing things to happen on posedge clock.

[fpgaboy.git] / Sound2.v

diff --git a/Sound2.v b/Sound2.v
index fa5e5e793c6ef664ee7b659ff42896cc58cd888e..cf8e83a72feb2952f18339bd82841db024d049da 100644 (file)
--- a/Sound2.v
+++ b/Sound2.v
@@ -16,7 +16,7 @@ module Sound2(
        );
 
        /* can be optimized as register file */
        );
 
        /* can be optimized as register file */

-       reg [7:0] nr21, nr22, nr23, nr24;
+       reg [7:0] nr21 = 0, nr22 = 0, nr23 = 0, nr24 = 0;

        reg [10:0] counter = 0;
        reg [4:0] lencnt = 0;
        reg [3:0] delta = 4'b1111;
        reg [10:0] counter = 0;
        reg [4:0] lencnt = 0;
        reg [3:0] delta = 4'b1111;


@@ -32,7 +32,7 @@ module Sound2(
                         addr == `ADDR_NR24 ? nr24 : 8'bzzzzzzzz
                      : 8'bzzzzzzzz;
 
                         addr == `ADDR_NR24 ? nr24 : 8'bzzzzzzzz
                      : 8'bzzzzzzzz;
 

-       always @ (negedge core_clk) begin
+       always @ (posedge core_clk) begin

                if(en && wr) begin
                        case(addr)
                        `ADDR_NR21: nr21 <= data;
                if(en && wr) begin
                        case(addr)
                        `ADDR_NR21: nr21 <= data;