`define INSN_NOP 8'b00000000
`define INSN_RST 8'b11xxx111
`define INSN_RET 8'b110x1001 // 1 = RETI, 0 = RET
+`define INSN_CALL 8'b11001101
`define INSN_reg_A 3'b111
`define INSN_reg_B 3'b000
reg [7:0] rdata, wdata; /* Read data from this bus cycle, or write data for the next. */
reg rd = 1, wr = 0, newcycle = 1;
- reg [7:0] tmp; /* Generic temporary reg. */
+ reg [7:0] tmp, tmp2; /* Generic temporary regs. */
reg [7:0] buswdata;
assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
end
endcase
end
+ `INSN_CALL: begin
+ case (cycle)
+ 0: begin
+ `EXEC_INC_PC;
+ `EXEC_NEXTADDR_PCINC;
+ rd <= 1;
+ end
+ 1: begin
+ `EXEC_INC_PC;
+ `EXEC_NEXTADDR_PCINC;
+ rd <= 1;
+ end
+ 2: begin
+ `EXEC_INC_PC;
+ end
+ 3: begin
+ address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
+ wdata <= registers[`REG_PCH];
+ wr <= 1;
+ end
+ 4: begin
+ address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
+ wdata <= registers[`REG_PCL];
+ wr <= 1;
+ end
+ 5: begin
+ `EXEC_NEWCYCLE; /* do NOT increment the PC */
+ end
+ endcase
+ end
default:
$stop;
endcase
end
endcase
end
+ `INSN_CALL: begin
+ case (cycle)
+ 0: cycle <= 1;
+ 1: begin
+ cycle <= 2;
+ tmp <= rdata; // tmp contains newpcl
+ end
+ 2: begin
+ cycle <= 3;
+ tmp2 <= rdata; // tmp2 contains newpch
+ end
+ 3: begin
+ cycle <= 4;
+ end
+ 4: begin
+ cycle <= 5;
+ registers[`REG_PCH] <= tmp2;
+ end
+ 5: begin
+ {registers[`REG_SPH],registers[`REG_SPL]} <=
+ {registers[`REG_SPH],registers[`REG_SPL]} - 2;
+ registers[`REG_PCL] <= tmp;
+ cycle <= 0;
+ end
+ endcase
+ end
+ default:
+ $stop;
endcase
state <= `STATE_FETCH;
end
endmodule
`timescale 1ns / 1ps
-module TestBench();
- reg clk = 0;
+module ROM(
+ input [15:0] address,
+ inout [7:0] data,
+ input clk,
+ input wr, rd);
+
+ reg [7:0] rom [2047:0];
+ initial $readmemh("rom.hex", rom);
+
+ wire decode = address[15:13] == 0;
+ wire [7:0] odata = rom[address[11:0]];
+ assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+ //assign data = rd ? odata : 8'bzzzzzzzz;
+endmodule
+
+module InternalRAM(
+ input [15:0] address,
+ inout [7:0] data,
+ input clk,
+ input wr, rd);
+
+ reg [7:0] ram [8191:0];
+
+ wire decode = (address >= 16'hC000) && (address < 16'hFE00);
+ reg [7:0] odata;
+ wire idata = data;
+ assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+
+ always @(negedge clk)
+ begin
+ if (decode && rd)
+ odata <= ram[address[12:0]];
+ else if (decode && wr)
+ ram[address[12:0]] <= data;
+ end
+endmodule
+
+//module Switches(
+// input [15:0] address,
+// inout [7:0] data,
+// input clk,
+// input wr, rd,
+// input [7:0] switches,
+// output reg [7:0] ledout);
+
+// wire decode = address == 16'hFF51;
+// reg [7:0] odata;
+// wire idata = data;
+// assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+
+// always @(negedge clk)
+// begin
+// if (decode && rd)
+// odata <= switches;
+// else if (decode && wr)
+// ledout <= data;
+// end
+//endmodule
+
+module CoreTop(
+ input iclk,
+ output wire [7:0] leds,
+ output serio);
+
+ wire clk;
+ IBUFG ibuf (.O(clk), .I(iclk));
+
wire [15:0] addr;
wire [7:0] data;
wire wr, rd;
- reg [7:0] rom [2047:0];
- initial $readmemh("rom.hex", rom);
- always #10 clk <= ~clk;
+ wire [7:0] swleds;
+
+ assign leds = clk?{rd,wr,addr[5:0]}:data[7:0];
+
GBZ80Core core(
.clk(clk),
.busaddress(addr),
.busdata(data),
.buswr(wr),
.busrd(rd));
- assign data = rd ? rom[addr] : 8'bzzzzzzzz;
+
+ ROM rom(
+ .address(addr),
+ .data(data),
+ .clk(clk),
+ .wr(wr),
+ .rd(rd));
+
+ assign serio = 0;
endmodule
+
+//module TestBench();
+// reg clk = 0;
+// wire [15:0] addr;
+// wire [7:0] data;
+// wire wr, rd;
+
+// wire [7:0] leds;
+// wire [7:0] switches;
+
+// always #10 clk <= ~clk;
+// GBZ80Core core(
+// .clk(clk),
+// .busaddress(addr),
+// .busdata(data),
+// .buswr(wr),
+// .busrd(rd));
+
+// ROM rom(
+// .clk(clk),
+// .address(addr),
+// .data(data),
+// .wr(wr),
+// .rd(rd));
+
+// InternalRAM ram(
+// .address(addr),
+// .data(data),
+// .clk(clk),
+// .wr(wr),
+// .rd(rd));
+
+// wire serio;
+// UART uart(
+// .addr(addr),
+// .data(data),
+// .clk(clk),
+// .wr(wr),
+// .rd(rd),
+// .serial(serio));
+
+// Switches sw(
+// .clk(clk),
+// .address(addr),
+// .data(data),
+// .wr(wr),
+// .rd(rd),
+// .switches(switches),
+// .leds(leds));
+//endmodule
git.joshuawise.com / fpgaboy.git / blobdiff