+module ROM(
+ input [15:0] address,
+ inout [7:0] data,
+ input clk,
+ input wr, rd);
+
+ reg [7:0] rom [2047:0];
+ initial $readmemh("rom.hex", rom);
+
+ wire decode = address[15:13] == 0;
+ wire [7:0] odata = rom[address[11:0]];
+ assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+ //assign data = rd ? odata : 8'bzzzzzzzz;
+endmodule
+
+module InternalRAM(
+ input [15:0] address,
+ inout [7:0] data,
+ input clk,
+ input wr, rd);
+
+ reg [7:0] ram [8191:0];
+
+ wire decode = (address >= 16'hC000) && (address < 16'hFE00);
+ reg [7:0] odata;
+ wire idata = data;
+ assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+
+ always @(negedge clk)
+ begin
+ if (decode && rd)
+ odata <= ram[address[12:0]];
+ else if (decode && wr)
+ ram[address[12:0]] <= data;
+ end
+endmodule
+
+//module Switches(
+// input [15:0] address,
+// inout [7:0] data,
+// input clk,
+// input wr, rd,
+// input [7:0] switches,
+// output reg [7:0] ledout);
+
+// wire decode = address == 16'hFF51;
+// reg [7:0] odata;
+// wire idata = data;
+// assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+
+// always @(negedge clk)
+// begin
+// if (decode && rd)
+// odata <= switches;
+// else if (decode && wr)
+// ledout <= data;
+// end
+//endmodule
+
+module CoreTop(
+ input iclk,
+ output wire [7:0] leds,
+ output serio);
+
+ wire clk;
+ IBUFG ibuf (.O(clk), .I(iclk));
+