Add cut 1 of a cellram module
[fpgaboy.git] / System.v
index 996ec10..4d0ddbb 100644 (file)
--- a/System.v
+++ b/System.v
@@ -6,13 +6,104 @@ module ROM(
        input clk,
        input wr, rd);
 
-       reg [7:0] rom [2047:0];
+       reg [7:0] odata;
+
+       // synthesis attribute ram_style of rom is block
+       reg [7:0] rom [1023:0];
        initial $readmemh("rom.hex", rom);
 
        wire decode = address[15:13] == 0;
-       wire [7:0] odata = rom[address[11:0]];
+       always @(posedge clk)
+               odata <= rom[address[10:0]];
+       assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+endmodule
+
+module BootstrapROM(
+       input [15:0] address,
+       inout [7:0] data,
+       input clk,
+       input wr, rd);
+
+       reg [7:0] brom [255:0];
+       initial $readmemh("bootstrap.hex", brom);
+
+       wire decode = address[15:8] == 0;
+       wire [7:0] odata = brom[address[7:0]];
+       assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+endmodule
+
+module MiniRAM(
+       input [15:0] address,
+       inout [7:0] data,
+       input clk,
+       input wr, rd);
+       
+       reg [7:0] ram [127:0];
+       
+       wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
+       reg [7:0] odata;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
-       //assign data = rd ? odata : 8'bzzzzzzzz;
+       
+       always @(posedge clk)
+       begin
+               if (decode)     // This has to go this way. The only way XST knows how to do
+               begin                           // block ram is chip select, write enable, and always
+                       if (wr)         // reading. "else if rd" does not cut it ...
+                               ram[address[6:0]] <= data;
+                       odata <= ram[address[6:0]];
+               end
+       end
+endmodule
+
+module CellularRAM(
+       input clk,
+       input [15:0] address,
+       inout [7:0] data,
+       input wr, rd,
+       output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
+       output wire [22:0] cr_A,
+       inout [15:0] cr_DQ);
+       
+       parameter ADDR_PROGADDRH = 16'hFF60;
+       parameter ADDR_PROGADDRM = 16'hFF61;
+       parameter ADDR_PROGADDRL = 16'hFF62;
+       parameter ADDR_PROGDATA = 16'hFF63;
+       
+       reg [7:0] progaddrh, progaddrm, progaddrl;
+       
+       assign cr_nADV = 0;     /* Addresses are always valid! :D */
+       assign cr_nCE = 0;      /* The chip is enabled */
+       assign cr_nLB = 0;      /* Lower byte is enabled */
+       assign cr_nUB = 0;      /* Upper byte is enabled */
+       assign cr_CRE = 0;      /* Data writes, not config */
+       assign cr_CLK = 0;      /* Clock? I think not! */
+       
+       wire decode = (address[15:14] == 2'b00) /* extrom */ || (address[15:13] == 3'b101) /* extram */ || (address == ADDR_PROGDATA);
+       
+       assign cr_nOE = decode ? ~rd : 1;
+       assign cr_nWE = decode ? ~wr : 1;
+       
+       assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, data};
+       assign cr_A = (address[15:14] == 2'b00) ? /* extrom */ {9'b0,address[13:0]} :
+                       (address[15:13] == 3'b101) ? {1'b1, 9'b0, address[12:0]} :
+                       (address == ADDR_PROGDATA) ? {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} :
+                       23'b0;
+       
+       reg [7:0] regbuf;
+       
+       always @(posedge clk)
+               case (address)
+               ADDR_PROGADDRH: if (wr) progaddrh <= data;
+               ADDR_PROGADDRM: if (wr) progaddrm <= data;
+               ADDR_PROGADDRL: if (wr) progaddrl <= data;
+               endcase
+       
+       assign data = (rd && decode) ?
+                               (address == ADDR_PROGADDRH) ? progaddrh :
+                               (address == ADDR_PROGADDRM) ? progaddrm :
+                               (address == ADDR_PROGADDRL) ? progaddrl :
+                               cr_DQ
+                       : 8'bzzzzzzzz;
 endmodule
 
 module InternalRAM(
@@ -21,19 +112,18 @@ module InternalRAM(
        input clk,
        input wr, rd);
        
-       // synthesis attribute ram_style of reg is block
+       // synthesis attribute ram_style of ram is block
        reg [7:0] ram [8191:0];
        
-       wire decode = address[15:13] == 3'b110;
+       wire decode = (address >= 16'hC000) && (address <= 16'hFDFF);   /* This includes echo RAM. */
        reg [7:0] odata;
-       wire idata = data;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
-       always @(negedge clk)
+       always @(posedge clk)
        begin
-               if (decode)
-               begin
-                       if (wr)
+               if (decode)             // This has to go this way. The only way XST knows how to do
+               begin                   // block ram is chip select, write enable, and always
+                       if (wr)         // reading. "else if rd" does not cut it ...
                                ram[address[12:0]] <= data;
                        odata <= ram[address[12:0]];
                end
@@ -46,13 +136,13 @@ module Switches(
        input clk,
        input wr, rd,
        input [7:0] switches,
-       output reg [7:0] ledout);
+       output reg [7:0] ledout = 0);
        
        wire decode = address == 16'hFF51;
        reg [7:0] odata;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
-       always @(negedge clk)
+       always @(posedge clk)
        begin
                if (decode && rd)
                        odata <= switches;
@@ -61,119 +151,215 @@ module Switches(
        end
 endmodule
 
+`ifdef isim
+module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
+endmodule
+`endif
+
 module CoreTop(
+`ifdef isim
+       output reg vgaclk = 0,
+       output reg clk = 0,
+`else
        input xtal,
        input [7:0] switches,
        input [3:0] buttons,
        output wire [7:0] leds,
        output serio,
        output wire [3:0] digits,
-       output wire [7:0] seven);
+       output wire [7:0] seven,
+       output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
+       output wire [22:0] cr_A,
+       inout [15:0] cr_DQ,
+`endif
+       output wire hs, vs,
+       output wire [2:0] r, g,
+       output wire [1:0] b,
+       output wire soundl, soundr);
+
+`ifdef isim
+       always #62 clk <= ~clk;
+       always #100 vgaclk <= ~vgaclk;
        
-       wire clk;
-       //IBUFG ibuf (.O(clk), .I(iclk));
+       Dumpable dump(r,g,b,hs,vs,vgaclk);
        
-       CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
-
-       wire [15:0] addr;       
-       wire [7:0] data;
-       wire wr, rd;
+       wire [7:0] leds;
+       wire serio;
+       wire [3:0] digits;
+       wire [7:0] seven;
+       wire [7:0] switches = 8'b0;
+       wire [3:0] buttons = 4'b0;
+`else  
+       wire xtalb, clk, vgaclk;
+       IBUFG iclkbuf(.O(xtalb), .I(xtal));
+       CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
+       pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
+`endif
 
+       wire [15:0] addr [1:0];
+       wire [7:0] data [1:0];
+       wire wr [1:0], rd [1:0];
+       
+       wire irq, tmrirq, lcdcirq, vblankirq;
+       wire [7:0] jaddr;
+       wire [1:0] state;
+       
        GBZ80Core core(
                .clk(clk),
-               .busaddress(addr),
-               .busdata(data),
-               .buswr(wr),
-               .busrd(rd));
+               .bus0address(addr[0]),
+               .bus0data(data[0]),
+               .bus0wr(wr[0]),
+               .bus0rd(rd[0]),
+               .bus1address(addr[1]),
+               .bus1data(data[1]),
+               .bus1wr(wr[1]),
+               .bus1rd(rd[1]),
+               .irq(irq),
+               .jaddr(jaddr),
+               .state(state));
        
+       BootstrapROM brom(
+               .address(addr[1]),
+               .data(data[1]),
+               .clk(clk),
+               .wr(wr[1]),
+               .rd(rd[1]));
+       
+`ifdef isim
        ROM rom(
-               .address(addr),
-               .data(data),
+               .address(addr[0]),
+               .data(data[0]),
+               .clk(clk),
+               .wr(wr[0]),
+               .rd(rd[0]));
+`else
+       CellularRAM cellram(
+               .address(addr[0]),
+               .data(data[0]),
                .clk(clk),
-               .wr(wr),
-               .rd(rd));
+               .wr(wr[0]),
+               .rd(rd[0])
+               .cr_nADV(cr_nADV),
+               .cr_nCE(cr_nCE),
+               .cr_nOE(cr_nOE),
+               .cr_nWR(cr_nWE),
+               .cr_CRE(cr_CRE),
+               .cr_nLB(cr_nLB),
+               .cr_nUB(cr_nUB),
+               .cr_CLK(cr_CLK),
+               .cr_A(cr_A),
+               .cr_DQ(cr_DQ));
+`endif
+       
+       wire lcdhs, lcdvs, lcdclk;
+       wire [2:0] lcdr, lcdg;
+       wire [1:0] lcdb;
+       
+       LCDC lcdc(
+               .clk(clk),
+               .addr(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0]),
+               .lcdcirq(lcdcirq),
+               .vblankirq(vblankirq),
+               .lcdclk(lcdclk),
+               .lcdhs(lcdhs),
+               .lcdvs(lcdvs),
+               .lcdr(lcdr),
+               .lcdg(lcdg),
+               .lcdb(lcdb));
+       
+       Framebuffer fb(
+               .lcdclk(lcdclk),
+               .lcdhs(lcdhs),
+               .lcdvs(lcdvs),
+               .lcdr(lcdr),
+               .lcdg(lcdg),
+               .lcdb(lcdb),
+               .vgaclk(vgaclk),
+               .vgahs(hs),
+               .vgavs(vs),
+               .vgar(r),
+               .vgag(g),
+               .vgab(b));
        
        AddrMon amon(
-    .addr(addr), 
-    .clk(clk), 
-    .digit(digits), 
-    .out(seven),
-        .freeze(buttons[0])
-    );
+               .clk(clk), 
+               .addr(addr[0]),
+               .digit(digits), 
+               .out(seven),
+               .freeze(buttons[0]),
+               .periods(
+                       (state == 2'b00) ? 4'b0010 :
+                       (state == 2'b01) ? 4'b0001 :
+                       (state == 2'b10) ? 4'b1000 :
+                                          4'b0100) );
         
        Switches sw(
-               .address(addr),
-               .data(data),
                .clk(clk),
-               .wr(wr),
-               .rd(rd),
+               .address(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0]),
                .ledout(leds),
                .switches(switches)
                );
 
-       UART nouart (
-    .clk(clk), 
-    .wr(wr), 
-    .rd(rd), 
-    .addr(addr), 
-    .data(data), 
-    .serial(serio)
-    );
-
-  InternalRAM ram(
-               .address(addr),
-               .data(data),
+       UART nouart (   /* no u */
                .clk(clk),
-               .wr(wr),
-               .rd(rd));
-endmodule
+               .addr(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0]),
+               .serial(serio)
+               );
 
-module TestBench();
-       reg clk = 0;
-       wire [15:0] addr;
-       wire [7:0] data;
-       wire wr, rd;
-       
-//     wire [7:0] leds;
-//     wire [7:0] switches;
-       
-       always #10 clk <= ~clk;
-       GBZ80Core core(
-               .clk(clk),
-               .busaddress(addr),
-               .busdata(data),
-               .buswr(wr),
-               .busrd(rd));
-       
-       ROM rom(
+       InternalRAM ram(
                .clk(clk),
-               .address(addr),
-               .data(data),
-               .wr(wr),
-               .rd(rd));
+               .address(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0])
+               );
        
-       InternalRAM ram(
-               .address(addr),
-               .data(data),
+       MiniRAM mram(
                .clk(clk),
-               .wr(wr),
-               .rd(rd));
+               .address(addr[1]),
+               .data(data[1]),
+               .wr(wr[1]),
+               .rd(rd[1])
+               );
 
-       wire serio;
-       UART uart(
-               .addr(addr),
-               .data(data),
+       Timer tmr(
                .clk(clk),
-               .wr(wr),
-               .rd(rd),
-               .serial(serio));
-       
-//     Switches sw(
-//             .clk(clk),
-//             .address(addr),
-//             .data(data),
-//             .wr(wr),
-//             .rd(rd),
-//             .switches(switches),
-//             .leds(leds));
+               .addr(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0]),
+               .irq(tmrirq)
+               );
+       
+       Interrupt intr(
+               .clk(clk),
+               .addr(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0]),
+               .vblank(vblankirq),
+               .lcdc(lcdcirq),
+               .tovf(tmrirq),
+               .serial(1'b0),
+               .buttons(1'b0),
+               .master(irq),
+               .jaddr(jaddr));
+       
+       Soundcore sound(
+               .core_clk(clk),
+               .addr(addr[0]),
+               .data(data[0]),
+               .rd(rd[0]),
+               .wr(wr[0]),
+               .snd_data_l(soundl),
+               .snd_data_r(soundr));
 endmodule
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