Wire switches back up and remove cclk.

[fpgaboy.git] / GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index f4383397978f92fd5539f45dd90b7c40ee1415fd..36cd76af6f6af77895762676654481cac11fc087 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -118,9 +118,10 @@ module GBZ80Core(
        output reg [15:0] busaddress,   /* BUS_* is latched on STATE_FETCH. */
        inout [7:0] busdata,
        output reg buswr, output reg busrd,
-       input irq, input [7:0] jaddr);
+       input irq, input [7:0] jaddr,
+       output reg [1:0] state);
        
-       reg [1:0] state;                                        /* State within this bus cycle (see STATE_*). */
+//     reg [1:0] state;                                        /* State within this bus cycle (see STATE_*). */
        reg [2:0] cycle;                                        /* Cycle for instructions. */
        
        reg [7:0] registers[11:0];