Make the boot rom talk a bit more, and wait for you to flip a switch. Make the 'progr...

[fpgaboy.git] / Uart.v

diff --git a/Uart.v b/Uart.v
index 07f996a6a475add8a984a934271bba2c36f25b56..e5213044f684b88f1812e011800883bebcf2bd69 100644 (file)
--- a/Uart.v
+++ b/Uart.v
@@ -1,7 +1,8 @@
 `define IN_CLK 8388608
 `define OUT_CLK 57600
 `define CLK_DIV `IN_CLK / `OUT_CLK
-`define MMAP_ADDR 16'hFF50
+`define DATA_ADDR 16'hFF52
+`define STAT_ADDR 16'hFF53
 
 module UART(
        input clk,
@@ -11,52 +12,51 @@ module UART(
        inout [7:0] data,
        output reg serial = 1);
 
-       reg rdlatch = 0;
-       wire decode = (addr == `MMAP_ADDR);
+       wire data_decode = (addr == `DATA_ADDR);
+       wire stat_decode = (addr == `STAT_ADDR);
+       reg data_latch = 0;
+       reg stat_latch = 0;
        
-       wire [7:0] odata;
-       assign data = rdlatch ? odata : 8'bzzzzzzzz;
-
-       reg [7:0] data_stor = 0;
-       reg [15:0] clkdiv = 0;
-       reg have_data = 0;
-       reg [3:0] diqing = 4'b0000;
-       
-       wire newdata = (wr) && (!have_data) && decode;
+       reg [7:0] tx_data = 0;
+       reg [15:0] tx_clkdiv = 0;
+       reg [3:0] tx_state = 4'b1011;   // 1011 is the not busy state.
+       wire tx_busy = tx_state != 4'b1011;
+       wire tx_newdata = (wr) && (!tx_busy) && data_decode;
        
-       assign odata = have_data ? 8'b1 : 8'b0;
+       assign data = (rd && stat_latch) ? (tx_busy ? 8'b1 : 8'b0) :
+                       (rd && data_latch) ? (8'b0) :
+                       8'bzzzzzzzz;
 
-       always @ (posedge clk)
+       always @(posedge clk)
        begin
-               rdlatch <= rd && decode;
+               data_latch <= rd && data_decode;
+               stat_latch <= rd && stat_decode;
                /* deal with diqing */
-               if(newdata) begin
-                       data_stor <= data;
-                       have_data <= 1;
-                       diqing <= 4'b0000;
-               end else if (clkdiv == 0) begin
-                       diqing <= diqing + 1;
-                       if (have_data)
-                               case (diqing)
+               if(tx_newdata) begin
+                       tx_data <= data;
+                       tx_state <= 4'b0000;
+               end else if (tx_clkdiv == 0) begin
+                       tx_state <= tx_state + 1;
+                       if (tx_busy)
+                               case (tx_state)
                                4'b0000: serial <= 0;
-                               4'b0001: serial <= data_stor[0];
-                               4'b0010: serial <= data_stor[1];
-                               4'b0011: serial <= data_stor[2];
-                               4'b0100: serial <= data_stor[3];
-                               4'b0101: serial <= data_stor[4];
-                               4'b0110: serial <= data_stor[5];
-                               4'b0111: serial <= data_stor[6];
-                               4'b1000: serial <= data_stor[7];
+                               4'b0001: serial <= tx_data[0];
+                               4'b0010: serial <= tx_data[1];
+                               4'b0011: serial <= tx_data[2];
+                               4'b0100: serial <= tx_data[3];
+                               4'b0101: serial <= tx_data[4];
+                               4'b0110: serial <= tx_data[5];
+                               4'b0111: serial <= tx_data[6];
+                               4'b1000: serial <= tx_data[7];
                                4'b1001: serial <= 1;
-                               4'b1010: have_data <= 0;
+                               4'b1010: serial <= 1;
                                default: $stop;
                        endcase
                end
 
-               /* deal with clkdiv */
-               if((newdata && !have_data) || clkdiv == `CLK_DIV)
-                       clkdiv <= 0;
+               if((tx_newdata && !tx_busy) || (tx_clkdiv == `CLK_DIV))
+                       tx_clkdiv <= 0;
                else
-                       clkdiv <= clkdiv + 1;
+                       tx_clkdiv <= tx_clkdiv + 1;
        end
 endmodule