`define IN_CLK 8388608
`define OUT_CLK 57600
`define CLK_DIV `IN_CLK / `OUT_CLK
`define DATA_ADDR 16'hFF52
`define STAT_ADDR 16'hFF53

module UART(
	input clk,
	input wr,
	input rd,
	input [15:0] addr,
	inout [7:0] data,
	output reg serial = 1);

	wire data_decode = (addr == `DATA_ADDR);
	wire stat_decode = (addr == `STAT_ADDR);
	reg data_latch = 0;
	reg stat_latch = 0;
	
	reg [7:0] tx_data = 0;
	reg [15:0] tx_clkdiv = 0;
	reg [3:0] tx_state = 4'b1011;	// 1011 is the not busy state.
	wire tx_busy = tx_state != 4'b1011;
	wire tx_newdata = (wr) && (!tx_busy) && data_decode;
	
	assign data = (rd && stat_latch) ? (tx_busy ? 8'b1 : 8'b0) :
			(rd && data_latch) ? (8'b0) :
			8'bzzzzzzzz;

	always @(posedge clk)
	begin
		data_latch <= rd && data_decode;
		stat_latch <= rd && stat_decode;
		/* deal with diqing */
		if(tx_newdata) begin
			tx_data <= data;
			tx_state <= 4'b0000;
		end else if (tx_clkdiv == 0) begin
			tx_state <= tx_state + 1;
			if (tx_busy)
				case (tx_state)
				4'b0000: serial <= 0;
				4'b0001: serial <= tx_data[0];
				4'b0010: serial <= tx_data[1];
				4'b0011: serial <= tx_data[2];
				4'b0100: serial <= tx_data[3];
				4'b0101: serial <= tx_data[4];
				4'b0110: serial <= tx_data[5];
				4'b0111: serial <= tx_data[6];
				4'b1000: serial <= tx_data[7];
				4'b1001: serial <= 1;
				4'b1010: serial <= 1;
				default: $stop;
			endcase
		end

		if((tx_newdata && !tx_busy) || (tx_clkdiv == `CLK_DIV))
			tx_clkdiv <= 0;
		else
			tx_clkdiv <= tx_clkdiv + 1;
	end
endmodule