Fix part of the indentation tragedy.

[fpgaboy.git] / GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 75f9722adecc13cec3680858096f4b04a7707a9e..338c2d7f3ea283261b7895adb96c2767b6f86770 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -35,6 +35,7 @@
 `define INSN_ALU8                              8'b10xxxxxx     // 10 xxx yyy
 `define INSN_NOP                               8'b00000000
 `define INSN_RST                               8'b11xxx111
 `define INSN_ALU8                              8'b10xxxxxx     // 10 xxx yyy
 `define INSN_NOP                               8'b00000000
 `define INSN_RST                               8'b11xxx111

+`define INSN_RET                               8'b110x1001     // 1 = RETI, 0 = RET

 
 `define INSN_reg_A             3'b111
 `define INSN_reg_B             3'b000
 
 `define INSN_reg_A             3'b111
 `define INSN_reg_B             3'b000


@@ -84,6 +85,8 @@ module GBZ80Core(
        reg [7:0] buswdata;
        assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
        
        reg [7:0] buswdata;
        assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
        

+       reg ie = 0;
+       

        initial begin
                registers[ 0] <= 0;
                registers[ 1] <= 0;
        initial begin
                registers[ 0] <= 0;
                registers[ 1] <= 0;


@@ -143,7 +146,7 @@ module GBZ80Core(
                                                `EXEC_NEXTADDR_PCINC;
                                                rd <= 1;
                                        end
                                                `EXEC_NEXTADDR_PCINC;
                                                rd <= 1;
                                        end

-                               1: begin
+                               1:      begin

                                                `EXEC_INC_PC;
                                                if (opcode[5:3] == `INSN_reg_dHL) begin
                                                        address <= {registers[`REG_H], registers[`REG_L]};
                                                `EXEC_INC_PC;
                                                if (opcode[5:3] == `INSN_reg_dHL) begin
                                                        address <= {registers[`REG_H], registers[`REG_L]};


@@ -154,7 +157,7 @@ module GBZ80Core(
                                                        `EXEC_NEWCYCLE;
                                                end
                                        end
                                                        `EXEC_NEWCYCLE;
                                                end
                                        end

-                               2: begin
+                               2:      begin

                                                `EXEC_NEWCYCLE;
                                        end
                                endcase
                                                `EXEC_NEWCYCLE;
                                        end
                                endcase


@@ -167,13 +170,13 @@ module GBZ80Core(
                                case (cycle)
                                0:      begin
                                                case (opcode[2:0])
                                case (cycle)
                                0:      begin
                                                case (opcode[2:0])

-                                               `INSN_reg_A:    begin wdata <= registers[`REG_A]; end
-                                               `INSN_reg_B:    begin wdata <= registers[`REG_B]; end
-                                               `INSN_reg_C:    begin wdata <= registers[`REG_C]; end
-                                               `INSN_reg_D:    begin wdata <= registers[`REG_D]; end
-                                               `INSN_reg_E:    begin wdata <= registers[`REG_E]; end
-                                               `INSN_reg_H:    begin wdata <= registers[`REG_H]; end
-                                               `INSN_reg_L:    begin wdata <= registers[`REG_L]; end
+                                               `INSN_reg_A:    wdata <= registers[`REG_A];
+                                               `INSN_reg_B:    wdata <= registers[`REG_B];
+                                               `INSN_reg_C:    wdata <= registers[`REG_C];
+                                               `INSN_reg_D:    wdata <= registers[`REG_D];
+                                               `INSN_reg_E:    wdata <= registers[`REG_E];
+                                               `INSN_reg_H:    wdata <= registers[`REG_H];
+                                               `INSN_reg_L:    wdata <= registers[`REG_L];

                                                endcase
                                                address <= {registers[`REG_H], registers[`REG_L]};
                                                wr <= 1; rd <= 0;
                                                endcase
                                                address <= {registers[`REG_H], registers[`REG_L]};
                                                wr <= 1; rd <= 0;


@@ -186,11 +189,11 @@ module GBZ80Core(
                        end
                        `INSN_LD_reg_HL: begin
                                case(cycle)
                        end
                        `INSN_LD_reg_HL: begin
                                case(cycle)

-                               0: begin
+                               0:      begin

                                                address <= {registers[`REG_H], registers[`REG_L]};
                                                rd <= 1;
                                        end
                                                address <= {registers[`REG_H], registers[`REG_L]};
                                                rd <= 1;
                                        end

-                               1: begin
+                               1:      begin

                                                tmp <= rdata;
                                                `EXEC_INC_PC;
                                                `EXEC_NEWCYCLE;
                                                tmp <= rdata;
                                                `EXEC_INC_PC;
                                                `EXEC_NEWCYCLE;


@@ -201,13 +204,13 @@ module GBZ80Core(
                                `EXEC_INC_PC;
                                `EXEC_NEWCYCLE;
                                case (opcode[2:0])
                                `EXEC_INC_PC;
                                `EXEC_NEWCYCLE;
                                case (opcode[2:0])

-                               `INSN_reg_A:    begin tmp <= registers[`REG_A]; end
-                               `INSN_reg_B:    begin tmp <= registers[`REG_B]; end
-                               `INSN_reg_C:    begin tmp <= registers[`REG_C]; end
-                               `INSN_reg_D:    begin tmp <= registers[`REG_D]; end
-                               `INSN_reg_E:    begin tmp <= registers[`REG_E]; end
-                               `INSN_reg_H:    begin tmp <= registers[`REG_H]; end
-                               `INSN_reg_L:    begin tmp <= registers[`REG_L]; end
+                               `INSN_reg_A:    tmp <= registers[`REG_A];
+                               `INSN_reg_B:    tmp <= registers[`REG_B];
+                               `INSN_reg_C:    tmp <= registers[`REG_C];
+                               `INSN_reg_D:    tmp <= registers[`REG_D];
+                               `INSN_reg_E:    tmp <= registers[`REG_E];
+                               `INSN_reg_H:    tmp <= registers[`REG_H];
+                               `INSN_reg_L:    tmp <= registers[`REG_L];

                                endcase
                        end
                        `INSN_LD_reg_imm16: begin
                                endcase
                        end
                        `INSN_LD_reg_imm16: begin


@@ -238,7 +241,7 @@ module GBZ80Core(
                        end
                        `INSN_PUSH_reg: begin   /* PUSH is 16 cycles! */
                                case (cycle)
                        end
                        `INSN_PUSH_reg: begin   /* PUSH is 16 cycles! */
                                case (cycle)

-                               0: begin
+                               0:      begin

                                                wr <= 1;
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
                                                case (opcode[5:4])
                                                wr <= 1;
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
                                                case (opcode[5:4])


@@ -248,7 +251,7 @@ module GBZ80Core(
                                                `INSN_stack_HL: wdata <= registers[`REG_H];
                                                endcase
                                        end
                                                `INSN_stack_HL: wdata <= registers[`REG_H];
                                                endcase
                                        end

-                               1: begin
+                               1:      begin

                                                wr <= 1;
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
                                                case (opcode[5:4])
                                                wr <= 1;
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
                                                case (opcode[5:4])


@@ -259,7 +262,7 @@ module GBZ80Core(
                                                endcase
                                        end
                                2:      begin /* TWIDDLE OUR FUCKING THUMBS! */ end
                                                endcase
                                        end
                                2:      begin /* TWIDDLE OUR FUCKING THUMBS! */ end

-                               3: begin
+                               3:      begin

                                                `EXEC_NEWCYCLE;
                                                `EXEC_INC_PC;
                                        end
                                                `EXEC_NEWCYCLE;
                                                `EXEC_INC_PC;
                                        end


@@ -267,15 +270,15 @@ module GBZ80Core(
                        end
                        `INSN_POP_reg: begin    /* POP is 12 cycles! */
                                case (cycle)
                        end
                        `INSN_POP_reg: begin    /* POP is 12 cycles! */
                                case (cycle)

-                               0: begin
+                               0:      begin

                                                rd <= 1;
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]};
                                        end
                                                rd <= 1;
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]};
                                        end

-                               1: begin
+                               1:      begin

                                                rd <= 1;
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]};
                                        end
                                                rd <= 1;
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]};
                                        end

-                               2: begin
+                               2:      begin

                                                `EXEC_NEWCYCLE;
                                                `EXEC_INC_PC;
                                        end
                                                `EXEC_NEWCYCLE;
                                                `EXEC_INC_PC;
                                        end


@@ -292,7 +295,7 @@ module GBZ80Core(
                                                        wdata <= registers[`REG_A];
                                                end
                                        end
                                                        wdata <= registers[`REG_A];
                                                end
                                        end

-                               1: begin
+                               1:      begin

                                                `EXEC_NEWCYCLE;
                                                `EXEC_INC_PC;
                                        end
                                                `EXEC_NEWCYCLE;
                                                `EXEC_INC_PC;
                                        end


@@ -300,7 +303,7 @@ module GBZ80Core(
                        end
                        `INSN_LDx_AHL: begin
                                case (cycle)
                        end
                        `INSN_LDx_AHL: begin
                                case (cycle)

-                               0: begin
+                               0:      begin

                                                address <= {registers[`REG_H],registers[`REG_L]};
                                                if (opcode[3]) begin    // LDx A, (HL)
                                                        rd <= 1;
                                                address <= {registers[`REG_H],registers[`REG_L]};
                                                if (opcode[3]) begin    // LDx A, (HL)
                                                        rd <= 1;


@@ -324,14 +327,14 @@ module GBZ80Core(
                                        `EXEC_NEWCYCLE;
                                        `EXEC_INC_PC;
                                        case (opcode[2:0])
                                        `EXEC_NEWCYCLE;
                                        `EXEC_INC_PC;
                                        case (opcode[2:0])

-                                       `INSN_reg_A:    begin tmp <= registers[`REG_A]; end
-                                       `INSN_reg_B:    begin tmp <= registers[`REG_B]; end
-                                       `INSN_reg_C:    begin tmp <= registers[`REG_C]; end
-                                       `INSN_reg_D:    begin tmp <= registers[`REG_D]; end
-                                       `INSN_reg_E:    begin tmp <= registers[`REG_E]; end
-                                       `INSN_reg_H:    begin tmp <= registers[`REG_H]; end
-                                       `INSN_reg_L:    begin tmp <= registers[`REG_L]; end
-                                       `INSN_reg_dHL:  begin tmp <= rdata; end
+                                       `INSN_reg_A:    tmp <= registers[`REG_A];
+                                       `INSN_reg_B:    tmp <= registers[`REG_B];
+                                       `INSN_reg_C:    tmp <= registers[`REG_C];
+                                       `INSN_reg_D:    tmp <= registers[`REG_D];
+                                       `INSN_reg_E:    tmp <= registers[`REG_E];
+                                       `INSN_reg_H:    tmp <= registers[`REG_H];
+                                       `INSN_reg_L:    tmp <= registers[`REG_L];
+                                       `INSN_reg_dHL:  tmp <= rdata;

                                        endcase
                                end
                        end
                                        endcase
                                end
                        end


@@ -341,24 +344,43 @@ module GBZ80Core(
                        end
                        `INSN_RST: begin
                                case (cycle)
                        end
                        `INSN_RST: begin
                                case (cycle)

-                               0: begin
+                               0:      begin
+                                               `EXEC_INC_PC;           // This goes FIRST in RST
+                                       end
+                               1:      begin

                                                wr <= 1;
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
                                                wdata <= registers[`REG_PCH];
                                        end
                                                wr <= 1;
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
                                                wdata <= registers[`REG_PCH];
                                        end

-                               1: begin
+                               2:      begin

                                                wr <= 1;
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]}-2;
                                                wdata <= registers[`REG_PCL];
                                        end
                                                wr <= 1;
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]}-2;
                                                wdata <= registers[`REG_PCL];
                                        end

-                               2:      begin /* wee */ end
-                               3: begin
+                               3:      begin

                                                `EXEC_NEWCYCLE;
                                                {registers[`REG_PCH],registers[`REG_PCL]} <=
                                                        {10'b0,opcode[5:3],3'b0};
                                        end
                                endcase
                        end
                                                `EXEC_NEWCYCLE;
                                                {registers[`REG_PCH],registers[`REG_PCL]} <=
                                                        {10'b0,opcode[5:3],3'b0};
                                        end
                                endcase
                        end

+                       `INSN_RET: begin
+                               case (cycle)
+                               0:      begin
+                                               rd <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]};
+                                       end
+                               1:      begin
+                                               rd <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1;
+                                       end
+                               2:      begin /* twiddle thumbs */ end
+                               3:      begin
+                                               `EXEC_NEWCYCLE;
+                                               // do NOT increment PC!
+                                       end
+                               endcase
+                       end

                        default:
                                $stop;
                        endcase
                        default:
                                $stop;
                        endcase


@@ -368,8 +390,8 @@ module GBZ80Core(
                        casex (opcode)
                        `INSN_LD_reg_imm8:
                                case (cycle)
                        casex (opcode)
                        `INSN_LD_reg_imm8:
                                case (cycle)

-                               0: cycle <= 1;
-                               1: case (opcode[5:3])
+                               0:      cycle <= 1;
+                               1:      case (opcode[5:3])

                                        `INSN_reg_A:    begin registers[`REG_A] <= rdata; cycle <= 0; end
                                        `INSN_reg_B:    begin registers[`REG_B] <= rdata; cycle <= 0; end
                                        `INSN_reg_C:    begin registers[`REG_C] <= rdata; cycle <= 0; end
                                        `INSN_reg_A:    begin registers[`REG_A] <= rdata; cycle <= 0; end
                                        `INSN_reg_B:    begin registers[`REG_B] <= rdata; cycle <= 0; end
                                        `INSN_reg_C:    begin registers[`REG_C] <= rdata; cycle <= 0; end


@@ -379,7 +401,7 @@ module GBZ80Core(
                                        `INSN_reg_L:    begin registers[`REG_L] <= rdata; cycle <= 0; end
                                        `INSN_reg_dHL:  cycle <= 2;
                                        endcase
                                        `INSN_reg_L:    begin registers[`REG_L] <= rdata; cycle <= 0; end
                                        `INSN_reg_dHL:  cycle <= 2;
                                        endcase

-                               2: cycle <= 0;
+                               2:      cycle <= 0;

                                endcase
                        `INSN_HALT: begin
                                /* Nothing needs happen here. */
                                endcase
                        `INSN_HALT: begin
                                /* Nothing needs happen here. */


@@ -387,8 +409,8 @@ module GBZ80Core(
                        end
                        `INSN_LD_HL_reg: begin
                                case (cycle)
                        end
                        `INSN_LD_HL_reg: begin
                                case (cycle)

-                               0: cycle <= 1;
-                               1: cycle <= 0;
+                               0:      cycle <= 1;
+                               1:      cycle <= 0;

                                endcase
                        end
                        `INSN_LD_reg_HL: begin
                                endcase
                        end
                        `INSN_LD_reg_HL: begin


@@ -396,13 +418,13 @@ module GBZ80Core(
                                0:      cycle <= 1;
                                1:      begin
                                                case (opcode[5:3])
                                0:      cycle <= 1;
                                1:      begin
                                                case (opcode[5:3])

-                                               `INSN_reg_A:    begin registers[`REG_A] <= tmp; end
-                                               `INSN_reg_B:    begin registers[`REG_B] <= tmp; end
-                                               `INSN_reg_C:    begin registers[`REG_C] <= tmp; end
-                                               `INSN_reg_D:    begin registers[`REG_D] <= tmp; end
-                                               `INSN_reg_E:    begin registers[`REG_E] <= tmp; end
-                                               `INSN_reg_H:    begin registers[`REG_H] <= tmp; end
-                                               `INSN_reg_L:    begin registers[`REG_L] <= tmp; end
+                                               `INSN_reg_A:    registers[`REG_A] <= tmp;
+                                               `INSN_reg_B:    registers[`REG_B] <= tmp;
+                                               `INSN_reg_C:    registers[`REG_C] <= tmp;
+                                               `INSN_reg_D:    registers[`REG_D] <= tmp;
+                                               `INSN_reg_E:    registers[`REG_E] <= tmp;
+                                               `INSN_reg_H:    registers[`REG_H] <= tmp;
+                                               `INSN_reg_L:    registers[`REG_L] <= tmp;

                                                endcase
                                                cycle <= 0;
                                        end
                                                endcase
                                                cycle <= 0;
                                        end


@@ -410,13 +432,13 @@ module GBZ80Core(
                        end
                        `INSN_LD_reg_reg: begin
                                case (opcode[5:3])
                        end
                        `INSN_LD_reg_reg: begin
                                case (opcode[5:3])

-                               `INSN_reg_A:    begin registers[`REG_A] <= tmp; end
-                               `INSN_reg_B:    begin registers[`REG_B] <= tmp; end
-                               `INSN_reg_C:    begin registers[`REG_C] <= tmp; end
-                               `INSN_reg_D:    begin registers[`REG_D] <= tmp; end
-                               `INSN_reg_E:    begin registers[`REG_E] <= tmp; end
-                               `INSN_reg_H:    begin registers[`REG_H] <= tmp; end
-                               `INSN_reg_L:    begin registers[`REG_L] <= tmp; end
+                               `INSN_reg_A:    registers[`REG_A] <= tmp;
+                               `INSN_reg_B:    registers[`REG_B] <= tmp;
+                               `INSN_reg_C:    registers[`REG_C] <= tmp;
+                               `INSN_reg_D:    registers[`REG_D] <= tmp;
+                               `INSN_reg_E:    registers[`REG_E] <= tmp;
+                               `INSN_reg_H:    registers[`REG_H] <= tmp;
+                               `INSN_reg_L:    registers[`REG_L] <= tmp;

                                endcase
                        end
                        `INSN_LD_reg_imm16: begin
                                endcase
                        end
                        `INSN_LD_reg_imm16: begin


@@ -588,7 +610,7 @@ module GBZ80Core(
                                case (cycle)
                                0:      cycle <= 1;
                                1:      cycle <= 2;
                                case (cycle)
                                0:      cycle <= 1;
                                1:      cycle <= 2;

-                               2: cycle <= 3;
+                               2:      cycle <= 3;

                                3:      begin
                                                cycle <= 0;
                                                {registers[`REG_SPH],registers[`REG_SPL]} <=
                                3:      begin
                                                cycle <= 0;
                                                {registers[`REG_SPH],registers[`REG_SPL]} <=


@@ -596,6 +618,26 @@ module GBZ80Core(
                                        end
                                endcase
                        end
                                        end
                                endcase
                        end

+                       `INSN_RET: begin
+                               case (cycle)
+                               0:      cycle <= 1;
+                               1:      begin
+                                               cycle <= 2;
+                                               registers[`REG_PCL] <= rdata;
+                                       end
+                               2:      begin
+                                               cycle <= 3;
+                                               registers[`REG_PCH] <= rdata;
+                                       end
+                               3:      begin
+                                               cycle <= 0;
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                                       {registers[`REG_SPH],registers[`REG_SPL]} + 2;
+                                               if (opcode[4])  /* RETI */
+                                                       ie <= 1;
+                                       end
+                               endcase
+                       end

                        endcase
                        state <= `STATE_FETCH;
                end
                        endcase
                        state <= `STATE_FETCH;
                end