Add cut 1 of a cellram module

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index dc70cc0d9d7a49cab58aec6a2ba9a8ae05e4070e..4d0ddbb914b2ce938013bb99eb380105fdbb4db7 100644 (file)
--- a/System.v
+++ b/System.v
@@ -6,16 +6,33 @@ module ROM(
        input clk,
        input wr, rd);
 
        input clk,
        input wr, rd);
 

+       reg [7:0] odata;
+
+       // synthesis attribute ram_style of rom is block

        reg [7:0] rom [1023:0];
        initial $readmemh("rom.hex", rom);
 
        wire decode = address[15:13] == 0;
        reg [7:0] rom [1023:0];
        initial $readmemh("rom.hex", rom);
 
        wire decode = address[15:13] == 0;

-       wire [7:0] odata = rom[address[10:0]];
+       always @(posedge clk)
+               odata <= rom[address[10:0]];

        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;

-       //assign data = rd ? odata : 8'bzzzzzzzz;

 endmodule
 
 endmodule
 

-module MiniRAM(                        /* XXX will need to go INSIDE the CPU for when we do DMA */
+module BootstrapROM(
+       input [15:0] address,
+       inout [7:0] data,
+       input clk,
+       input wr, rd);
+
+       reg [7:0] brom [255:0];
+       initial $readmemh("bootstrap.hex", brom);
+
+       wire decode = address[15:8] == 0;
+       wire [7:0] odata = brom[address[7:0]];
+       assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+endmodule
+
+module MiniRAM(

        input [15:0] address,
        inout [7:0] data,
        input clk,
        input [15:0] address,
        inout [7:0] data,
        input clk,


@@ -27,7 +44,7 @@ module MiniRAM(                       /* XXX will need to go INSIDE the CPU for when we do DMA */
        reg [7:0] odata;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
        reg [7:0] odata;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        

-       always @(negedge clk)
+       always @(posedge clk)

        begin
                if (decode)     // This has to go this way. The only way XST knows how to do
                begin                           // block ram is chip select, write enable, and always
        begin
                if (decode)     // This has to go this way. The only way XST knows how to do
                begin                           // block ram is chip select, write enable, and always


@@ -38,6 +55,57 @@ module MiniRAM(                      /* XXX will need to go INSIDE the CPU for when we do DMA */
        end
 endmodule
 
        end
 endmodule
 

+module CellularRAM(
+       input clk,
+       input [15:0] address,
+       inout [7:0] data,
+       input wr, rd,
+       output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
+       output wire [22:0] cr_A,
+       inout [15:0] cr_DQ);
+       
+       parameter ADDR_PROGADDRH = 16'hFF60;
+       parameter ADDR_PROGADDRM = 16'hFF61;
+       parameter ADDR_PROGADDRL = 16'hFF62;
+       parameter ADDR_PROGDATA = 16'hFF63;
+       
+       reg [7:0] progaddrh, progaddrm, progaddrl;
+       
+       assign cr_nADV = 0;     /* Addresses are always valid! :D */
+       assign cr_nCE = 0;      /* The chip is enabled */
+       assign cr_nLB = 0;      /* Lower byte is enabled */
+       assign cr_nUB = 0;      /* Upper byte is enabled */
+       assign cr_CRE = 0;      /* Data writes, not config */
+       assign cr_CLK = 0;      /* Clock? I think not! */
+       
+       wire decode = (address[15:14] == 2'b00) /* extrom */ || (address[15:13] == 3'b101) /* extram */ || (address == ADDR_PROGDATA);
+       
+       assign cr_nOE = decode ? ~rd : 1;
+       assign cr_nWE = decode ? ~wr : 1;
+       
+       assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, data};
+       assign cr_A = (address[15:14] == 2'b00) ? /* extrom */ {9'b0,address[13:0]} :
+                       (address[15:13] == 3'b101) ? {1'b1, 9'b0, address[12:0]} :
+                       (address == ADDR_PROGDATA) ? {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} :
+                       23'b0;
+       
+       reg [7:0] regbuf;
+       
+       always @(posedge clk)
+               case (address)
+               ADDR_PROGADDRH: if (wr) progaddrh <= data;
+               ADDR_PROGADDRM: if (wr) progaddrm <= data;
+               ADDR_PROGADDRL: if (wr) progaddrl <= data;
+               endcase
+       
+       assign data = (rd && decode) ?
+                               (address == ADDR_PROGADDRH) ? progaddrh :
+                               (address == ADDR_PROGADDRM) ? progaddrm :
+                               (address == ADDR_PROGADDRL) ? progaddrl :
+                               cr_DQ
+                       : 8'bzzzzzzzz;
+endmodule
+

 module InternalRAM(
        input [15:0] address,
        inout [7:0] data,
 module InternalRAM(
        input [15:0] address,
        inout [7:0] data,


@@ -47,14 +115,14 @@ module InternalRAM(
        // synthesis attribute ram_style of ram is block
        reg [7:0] ram [8191:0];
        
        // synthesis attribute ram_style of ram is block
        reg [7:0] ram [8191:0];
        

-       wire decode = address[15:13] == 3'b110;
+       wire decode = (address >= 16'hC000) && (address <= 16'hFDFF);   /* This includes echo RAM. */

        reg [7:0] odata;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
        reg [7:0] odata;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        

-       always @(negedge clk)
+       always @(posedge clk)

        begin
        begin

-               if (decode)     // This has to go this way. The only way XST knows how to do
-               begin                           // block ram is chip select, write enable, and always
+               if (decode)             // This has to go this way. The only way XST knows how to do
+               begin                   // block ram is chip select, write enable, and always

                        if (wr)         // reading. "else if rd" does not cut it ...
                                ram[address[12:0]] <= data;
                        odata <= ram[address[12:0]];
                        if (wr)         // reading. "else if rd" does not cut it ...
                                ram[address[12:0]] <= data;
                        odata <= ram[address[12:0]];


@@ -74,7 +142,7 @@ module Switches(
        reg [7:0] odata;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
        reg [7:0] odata;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        

-       always @(negedge clk)
+       always @(posedge clk)

        begin
                if (decode && rd)
                        odata <= switches;
        begin
                if (decode && rd)
                        odata <= switches;


@@ -83,7 +151,16 @@ module Switches(
        end
 endmodule
 
        end
 endmodule
 

+`ifdef isim
+module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
+endmodule
+`endif
+

 module CoreTop(
 module CoreTop(

+`ifdef isim
+       output reg vgaclk = 0,
+       output reg clk = 0,
+`else

        input xtal,
        input [7:0] switches,
        input [3:0] buttons,
        input xtal,
        input [7:0] switches,
        input [3:0] buttons,


@@ -91,19 +168,37 @@ module CoreTop(
        output serio,
        output wire [3:0] digits,
        output wire [7:0] seven,
        output serio,
        output wire [3:0] digits,
        output wire [7:0] seven,

+       output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
+       output wire [22:0] cr_A,
+       inout [15:0] cr_DQ,
+`endif

        output wire hs, vs,
        output wire [2:0] r, g,
        output wire [1:0] b,
        output wire soundl, soundr);
        output wire hs, vs,
        output wire [2:0] r, g,
        output wire [1:0] b,
        output wire soundl, soundr);

+
+`ifdef isim
+       always #62 clk <= ~clk;
+       always #100 vgaclk <= ~vgaclk;

        
        

+       Dumpable dump(r,g,b,hs,vs,vgaclk);
+       
+       wire [7:0] leds;
+       wire serio;
+       wire [3:0] digits;
+       wire [7:0] seven;
+       wire [7:0] switches = 8'b0;
+       wire [3:0] buttons = 4'b0;
+`else  

        wire xtalb, clk, vgaclk;
        IBUFG iclkbuf(.O(xtalb), .I(xtal));
        CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
        pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
        wire xtalb, clk, vgaclk;
        IBUFG iclkbuf(.O(xtalb), .I(xtal));
        CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
        pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));

-       
-       wire [15:0] addr;       
-       wire [7:0] data;
-       wire wr, rd;
+`endif
+
+       wire [15:0] addr [1:0];
+       wire [7:0] data [1:0];
+       wire wr [1:0], rd [1:0];

        
        wire irq, tmrirq, lcdcirq, vblankirq;
        wire [7:0] jaddr;
        
        wire irq, tmrirq, lcdcirq, vblankirq;
        wire [7:0] jaddr;


@@ -111,31 +206,61 @@ module CoreTop(
        
        GBZ80Core core(
                .clk(clk),
        
        GBZ80Core core(
                .clk(clk),

-               .busaddress(addr),
-               .busdata(data),
-               .buswr(wr),
-               .busrd(rd),
+               .bus0address(addr[0]),
+               .bus0data(data[0]),
+               .bus0wr(wr[0]),
+               .bus0rd(rd[0]),
+               .bus1address(addr[1]),
+               .bus1data(data[1]),
+               .bus1wr(wr[1]),
+               .bus1rd(rd[1]),

                .irq(irq),
                .jaddr(jaddr),
                .state(state));
        
                .irq(irq),
                .jaddr(jaddr),
                .state(state));
        

+       BootstrapROM brom(
+               .address(addr[1]),
+               .data(data[1]),
+               .clk(clk),
+               .wr(wr[1]),
+               .rd(rd[1]));
+       
+`ifdef isim

        ROM rom(
        ROM rom(

-               .address(addr),
-               .data(data),
+               .address(addr[0]),
+               .data(data[0]),
+               .clk(clk),
+               .wr(wr[0]),
+               .rd(rd[0]));
+`else
+       CellularRAM cellram(
+               .address(addr[0]),
+               .data(data[0]),

                .clk(clk),
                .clk(clk),

-               .wr(wr),
-               .rd(rd));
+               .wr(wr[0]),
+               .rd(rd[0])
+               .cr_nADV(cr_nADV),
+               .cr_nCE(cr_nCE),
+               .cr_nOE(cr_nOE),
+               .cr_nWR(cr_nWE),
+               .cr_CRE(cr_CRE),
+               .cr_nLB(cr_nLB),
+               .cr_nUB(cr_nUB),
+               .cr_CLK(cr_CLK),
+               .cr_A(cr_A),
+               .cr_DQ(cr_DQ));
+`endif

        
        wire lcdhs, lcdvs, lcdclk;
        wire [2:0] lcdr, lcdg;
        wire [1:0] lcdb;
        
        LCDC lcdc(
        
        wire lcdhs, lcdvs, lcdclk;
        wire [2:0] lcdr, lcdg;
        wire [1:0] lcdb;
        
        LCDC lcdc(

-               .addr(addr),
-               .data(data),

                .clk(clk),
                .clk(clk),

-               .wr(wr),
-               .rd(rd),
+               .addr(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0]),

                .lcdcirq(lcdcirq),
                .vblankirq(vblankirq),
                .lcdclk(lcdclk),
                .lcdcirq(lcdcirq),
                .vblankirq(vblankirq),
                .lcdclk(lcdclk),


@@ -160,8 +285,8 @@ module CoreTop(
                .vgab(b));
        
        AddrMon amon(
                .vgab(b));
        
        AddrMon amon(

-               .addr(addr), 

                .clk(clk), 
                .clk(clk), 

+               .addr(addr[0]),

                .digit(digits), 
                .out(seven),
                .freeze(buttons[0]),
                .digit(digits), 
                .out(seven),
                .freeze(buttons[0]),


@@ -172,146 +297,69 @@ module CoreTop(
                                           4'b0100) );
         
        Switches sw(
                                           4'b0100) );
         
        Switches sw(

-               .address(addr),
-               .data(data),

                .clk(clk),
                .clk(clk),

-               .wr(wr),
-               .rd(rd),
+               .address(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0]),

                .ledout(leds),
                .switches(switches)
                );
 
        UART nouart (   /* no u */
                .ledout(leds),
                .switches(switches)
                );
 
        UART nouart (   /* no u */

-               .clk(clk), 
-               .wr(wr), 
-               .rd(rd), 
-               .addr(addr), 
-               .data(data), 
+               .clk(clk),
+               .addr(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0]),

                .serial(serio)
                );
 
        InternalRAM ram(
                .serial(serio)
                );
 
        InternalRAM ram(

-               .address(addr),
-               .data(data),

                .clk(clk),
                .clk(clk),

-               .wr(wr),
-               .rd(rd)
+               .address(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0])

                );
        
        MiniRAM mram(
                );
        
        MiniRAM mram(

-               .address(addr),
-               .data(data),

                .clk(clk),
                .clk(clk),

-               .wr(wr),
-               .rd(rd)
+               .address(addr[1]),
+               .data(data[1]),
+               .wr(wr[1]),
+               .rd(rd[1])

                );
 
        Timer tmr(
                .clk(clk),
                );
 
        Timer tmr(
                .clk(clk),

-               .wr(wr),
-               .rd(rd),
-               .addr(addr),
-               .data(data),
+               .addr(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0]),

                .irq(tmrirq)
                );
        
        Interrupt intr(
                .clk(clk),
                .irq(tmrirq)
                );
        
        Interrupt intr(
                .clk(clk),

-               .rd(rd),
-               .wr(wr),
-               .addr(addr),
-               .data(data),
+               .addr(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0]),

                .vblank(vblankirq),
                .lcdc(lcdcirq),
                .tovf(tmrirq),
                .vblank(vblankirq),
                .lcdc(lcdcirq),
                .tovf(tmrirq),

-               .serial(0),
-               .buttons(0),
+               .serial(1'b0),
+               .buttons(1'b0),

                .master(irq),
                .jaddr(jaddr));
        
        Soundcore sound(
                .core_clk(clk),
                .master(irq),
                .jaddr(jaddr));
        
        Soundcore sound(
                .core_clk(clk),

-               .rd(rd),
-               .wr(wr),
-               .addr(addr),
-               .data(data),
+               .addr(addr[0]),
+               .data(data[0]),
+               .rd(rd[0]),
+               .wr(wr[0]),

                .snd_data_l(soundl),
                .snd_data_r(soundr));
 endmodule
                .snd_data_l(soundl),
                .snd_data_r(soundr));
 endmodule

-
-module TestBench();
-       reg clk = 1;
-       wire [15:0] addr;
-       wire [7:0] data;
-       wire wr, rd;
-       
-       wire irq, tmrirq;
-       wire [7:0] jaddr;
-       
-       wire [7:0] leds;
-       wire [7:0] switches;
-       
-       always #62 clk <= ~clk;
-       GBZ80Core core(
-               .clk(clk),
-               .busaddress(addr),
-               .busdata(data),
-               .buswr(wr),
-               .busrd(rd),
-               .irq(irq),
-               .jaddr(jaddr));
-       
-       ROM rom(
-               .clk(clk),
-               .address(addr),
-               .data(data),
-               .wr(wr),
-               .rd(rd));
-       
-       InternalRAM ram(
-               .address(addr),
-               .data(data),
-               .clk(clk),
-               .wr(wr),
-               .rd(rd));
-
-       wire serio;
-       UART uart(
-               .addr(addr),
-               .data(data),
-               .clk(clk),
-               .wr(wr),
-               .rd(rd),
-               .serial(serio));
-       
-       Timer tmr(
-               .clk(clk),
-               .wr(wr),
-               .rd(rd),
-               .addr(addr),
-               .data(data),
-               .irq(tmrirq));
-       
-       Interrupt intr(
-               .clk(clk),
-               .rd(rd),
-               .wr(wr),
-               .addr(addr),
-               .data(data),
-               .vblank(0),
-               .lcdc(0),
-               .tovf(tmrirq),
-               .serial(0),
-               .buttons(0),
-               .master(irq),
-               .jaddr(jaddr));
-       
-       Switches sw(
-               .clk(clk),
-               .address(addr),
-               .data(data),
-               .wr(wr),
-               .rd(rd),
-               .switches(switches),
-               .ledout(leds));
-endmodule