Start changing things to happen on posedge clock.

[fpgaboy.git] / Timer.v

diff --git a/Timer.v b/Timer.v
index 0481614f5c97586672ba16ed34265b0dcc04b4da..e46b38bbaf937d7366c8fdb903ff84a0ce6ddeeb 100644 (file)
--- a/Timer.v
+++ b/Timer.v
@@ -9,11 +9,11 @@ module Timer(
        input rd,
        input [15:0] addr,
        inout [7:0] data,
-       output reg irq);
+       output reg irq = 0);
 
        reg [7:0] tima = 0, tma = 0, tac = 0, div = 0;
        reg ovf = 0;
-       reg [9:0] clkdv;
+       reg [9:0] clkdv = 0;
 
        wire is_tima = addr == `ADDR_TIMA;
        wire is_tma  = addr == `ADDR_TMA;
@@ -33,7 +33,7 @@ module Timer(
                        (clkdv[7:0] == 8'b0) :
                     0;
 
-       always @ (negedge clk) 
+       always @ (posedge clk) 
        begin
                if(wr) begin
                        case(addr)