Start changing things to happen on posedge clock.

[fpgaboy.git] / Soundcore.v

diff --git a/Soundcore.v b/Soundcore.v
index b2c4d35288f8f87897115d36cad85a44418741ea..626001ddd31b6050dec257a75372bb171a8baa35 100644 (file)
--- a/Soundcore.v
+++ b/Soundcore.v
@@ -12,9 +12,9 @@ module Soundcore(
        output reg snd_data_r
        );
 
-       reg [7:0] nr50,nr51,nr52;
-       reg [3:0] pwmcnt;
-       reg [4:0] cntclk;
+       reg [7:0] nr50 = 8'h00, nr51 = 8'h00, nr52 = 8'hF0;
+       reg [3:0] pwmcnt = 4'b0000;
+       reg [4:0] cntclk = 5'b00000;
        reg [13:0] lenclk;
        wire [3:0] sndout1,sndout2,sndout3,sndout4;
        wire [3:0] right_snd =
@@ -36,7 +36,7 @@ module Soundcore(
                         addr == `ADDR_NR52 ? nr52 : 8'bzzzzzzzz
                      : 8'bzzzzzzzz;
 
-       always @ (negedge core_clk) begin
+       always @ (posedge core_clk) begin
                if(wr) begin
                        case(addr)
                        `ADDR_NR50: nr50 <= data;
@@ -47,8 +47,8 @@ module Soundcore(
                cntclk <= cntclk + 1;
                lenclk <= lenclk + 1;
                pwmcnt <= pwmcnt + 1; 
-               snd_data_l <= (pwmcnt <= left_snd) ? nr50[7] : 0;
-               snd_data_r <= (pwmcnt <= right_snd) ? nr50[3] : 0;
+               snd_data_l <= (pwmcnt <= left_snd) ? 1 : 0;
+               snd_data_r <= (pwmcnt <= right_snd) ? 1 : 0;
        end
 
        Sound1 s1(