Start changing things to happen on posedge clock.

[fpgaboy.git] / Sound2.v

diff --git a/Sound2.v b/Sound2.v
index 2bb959861dcd9f5ebf48bc64b4bda1e02b490e63..cf8e83a72feb2952f18339bd82841db024d049da 100644 (file)
--- a/Sound2.v
+++ b/Sound2.v
@@ -32,7 +32,7 @@ module Sound2(
                         addr == `ADDR_NR24 ? nr24 : 8'bzzzzzzzz
                      : 8'bzzzzzzzz;
 
-       always @ (negedge core_clk) begin
+       always @ (posedge core_clk) begin
                if(en && wr) begin
                        case(addr)
                        `ADDR_NR21: nr21 <= data;