Joshua Wise's Git repositories - fpgaboy.git/blob

1 `timescale 1ns / 1ps

2

3 module SimROM(

4 input [15:0] address,

5 inout [7:0] data,

6 input clk,

7 input wr, rd);

8

9 reg rdlatch = 0;

10 reg [7:0] odata;

11

12 reg [7:0] rom [32767:0];

13 initial $readmemh("rom.hex", rom);

14

15 wire decode = address[15:13] == 0;

16 always @(posedge clk) begin

17 rdlatch <= rd && decode;

18 odata <= rom[address[10:0]];

19 end

20 assign data = rdlatch ? odata : 8'bzzzzzzzz;

21 endmodule

22

23 module BootstrapROM(

24 input [15:0] address,

25 inout [7:0] data,

26 input clk,

27 input wr, rd);

28

29 reg rdlatch = 0;

30 reg [7:0] addrlatch = 0;

31 reg romno = 0, romnotmp = 0;

32 reg [7:0] brom0 [255:0];

33 reg [7:0] brom1 [255:0];

34

35 initial $readmemh("fpgaboot.hex", brom0);

36 initial $readmemh("gbboot.hex", brom1);

37

38 `ifdef isim

39 initial romno <= 1;

40 `endif

41

42 wire decode = address[15:8] == 0;

43 wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];

44 always @(posedge clk) begin

45 rdlatch <= rd && decode;

46 addrlatch <= address[7:0];

47 if (wr && decode) romnotmp <= data[0];

48 if (rd && address == 16'h0000) romno <= romnotmp; /* Latch when the program restarts. */

49 end

50 assign data = rdlatch ? odata : 8'bzzzzzzzz;

51 endmodule

52

53 module MiniRAM(

54 input [15:0] address,

55 inout [7:0] data,

56 input clk,

57 input wr, rd);

58

59 reg [7:0] ram [127:0];

60

61 wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);

62 reg rdlatch = 0;

63 reg [7:0] odata;

64 assign data = rdlatch ? odata : 8'bzzzzzzzz;

65

66 always @(posedge clk)

67 begin

68 rdlatch <= rd && decode;

69 if (decode) // This has to go this way. The only way XST knows how to do

70 begin // block ram is chip select, write enable, and always

71 if (wr) // reading. "else if rd" does not cut it ...

72 ram[address[6:0]] <= data;

73 odata <= ram[address[6:0]];

74 end

75 end

76 endmodule

77

78 module CellularRAM(

79 input clk,

80 input [15:0] address,

81 inout [7:0] data,

82 input wr, rd,

83 output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,

84 output wire st_nCE, st_nRST,

85 output wire [22:0] cr_A,

86 inout [15:0] cr_DQ);

87

88 parameter ADDR_PROGADDRH = 16'hFF60;

89 parameter ADDR_PROGADDRM = 16'hFF61;

90 parameter ADDR_PROGADDRL = 16'hFF62;

91 parameter ADDR_PROGDATA = 16'hFF63;

92 parameter ADDR_PROGFLASH = 16'hFF65;

93 parameter ADDR_MBC = 16'hFF64;

94

95 reg rdlatch = 0, wrlatch = 0;

96 reg [15:0] addrlatch = 0;

97 reg [7:0] datalatch = 0;

98

99 reg [7:0] progaddrh, progaddrm, progaddrl;

100

101 reg [22:0] progaddr;

102

103 reg [7:0] mbc_emul = 8'b00000101; // High bit is whether we're poking flash

104 // low 7 bits are the MBC that we are emulating

105

106 assign cr_nADV = 0; /* Addresses are always valid! :D */

107 assign cr_nCE = ~(addrlatch != ADDR_PROGFLASH); /* The chip is enabled */

108 assign cr_nLB = 0; /* Lower byte is enabled */

109 assign cr_nUB = 0; /* Upper byte is enabled */

110 assign cr_CRE = 0; /* Data writes, not config */

111 assign cr_CLK = 0; /* Clock? I think not! */

112

113 assign st_nRST = 1; /* Keep the strataflash out of reset. */

114 assign st_nCE = ~(addrlatch == ADDR_PROGFLASH);

115

116 wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH);

117

118 reg [3:0] rambank = 0;

119 reg [8:0] rombank = 1;

120

121 assign cr_nOE = decode ? ~rdlatch : 1;

122 assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH) || (mbc_emul[6:0] == 0) || (addrlatch[15:13] == 3'b101))) ? ~wrlatch : 1;

123

124 assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};

125 assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom, home bank */ {9'b0,addrlatch[13:0]} :

126 (addrlatch[15:14] == 2'b01) ? /* extrom, paged bank */ {rombank, addrlatch[13:0]} :

127 (addrlatch[15:13] == 3'b101) ? /* extram */ {1'b1, 5'b0, rambank, addrlatch[12:0]} :

128 ((addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH)) ? progaddr :

129 23'b0;

130

131 always @(posedge clk) begin

132 case (address)

133 ADDR_PROGADDRH: if (wr) progaddrh <= data;

134 ADDR_PROGADDRM: if (wr) progaddrm <= data;

135 ADDR_PROGADDRL: if (wr) progaddrl <= data;

136 ADDR_PROGDATA: if (rd || wr) begin

137 progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};

138 {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;

139 end

140 ADDR_PROGFLASH: if (rd || wr) begin

141 progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};

142 {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;

143 end

144 ADDR_MBC: begin

145 mbc_emul <= data;

146 rambank <= 0;

147 rombank <= 1;

148 end

149 endcase

150

151 if (mbc_emul[6:0] == 5) begin

152 if ((address[15:12] == 4'h2) && wr)

153 rombank <= {rombank[8], data};

154 else if ((address[15:12] == 4'h3) && wr)

155 rombank <= {data[0], rombank[7:0]};

156 else if ((address[15:12] == 4'h4) && wr)

157 rambank <= data[3:0];

158 end

159

160 rdlatch <= rd;

161 wrlatch <= wr;

162 addrlatch <= address;

163 datalatch <= data;

164 end

165

166 assign data = (rdlatch && decode) ?

167 (addrlatch == ADDR_PROGADDRH) ? progaddrh :

168 (addrlatch == ADDR_PROGADDRM) ? progaddrm :

169 (addrlatch == ADDR_PROGADDRL) ? progaddrl :

170 cr_DQ

171 : 8'bzzzzzzzz;

172 endmodule

173

174 module InternalRAM(

175 input [15:0] address,

176 inout [7:0] data,

177 input clk,

178 input wr, rd);

179

180 // synthesis attribute ram_style of ram is block

181 reg [7:0] ram [8191:0];

182

183 wire decode = (address >= 16'hC000) && (address <= 16'hFDFF); /* This includes echo RAM. */

184 reg [7:0] odata;

185 reg rdlatch = 0;

186 assign data = rdlatch ? odata : 8'bzzzzzzzz;

187

188 always @(posedge clk)

189 begin

190 rdlatch <= rd && decode;

191 if (decode) // This has to go this way. The only way XST knows how to do

192 begin // block ram is chip select, write enable, and always

193 if (wr) // reading. "else if rd" does not cut it ...

194 ram[address[12:0]] <= data;

195 odata <= ram[address[12:0]];

196 end

197 end

198 endmodule

199

200 module Switches(

201 input [15:0] address,

202 inout [7:0] data,

203 input clk,

204 input wr, rd,

205 input [7:0] switches,

206 output reg [7:0] ledout = 0);

207

208 wire decode = address == 16'hFF51;

209 reg [7:0] odata;

210 reg rdlatch = 0;

211 assign data = rdlatch ? odata : 8'bzzzzzzzz;

212

213 always @(posedge clk)

214 begin

215 rdlatch <= rd && decode;

216 if (decode && rd)

217 odata <= switches;

218 else if (decode && wr)

219 ledout <= data;

220 end

221 endmodule

222

223 `ifdef isim

224 module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);

225 endmodule

226 `endif

227

228 module CoreTop(

229 `ifdef isim

230 output reg vgaclk = 0,

231 output reg clk = 0,

232 `else

233 input xtal,

234 input [7:0] switches,

235 input [3:0] buttons,

236 output wire [7:0] leds,

237 output serio,

238 input serin,

239 output wire [3:0] digits,

240 output wire [7:0] seven,

241 output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK, st_nCE, st_nRST,

242 output wire [22:0] cr_A,

243 inout [15:0] cr_DQ,

244 input ps2c, ps2d,

245 output txp, txm,

246 input rxp, rxm,

247 `endif

248 output wire hs, vs,

249 output wire [2:0] r, g,

250 output wire [1:0] b,

251 output wire soundl, soundr);

252

253 `ifdef isim

254 always #62 clk <= ~clk;

255 always #100 vgaclk <= ~vgaclk;

256

257 Dumpable dump(r,g,b,hs,vs,vgaclk);

258

259 wire [7:0] leds;

260 wire serio;

261 wire serin = 1;

262 wire [3:0] digits;

263 wire [7:0] seven;

264 wire [7:0] switches = 8'b0;

265 wire [3:0] buttons = 4'b0;

266 `else

267 wire xtalb, clk, vgaclk, ethclk;

268 IBUFG iclkbuf(.O(xtalb), .I(xtal));

269 CPUDCM cpudcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));

270 pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));

271 ethDCM ethdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(ethclk));

272 wire [7:0] ps2buttons;

273 `endif

274

275 wire [15:0] addr [1:0];

276 wire [7:0] data [1:0];

277 wire wr [1:0], rd [1:0];

278

279 wire irq, tmrirq, lcdcirq, vblankirq, btnirq;

280 wire [7:0] jaddr;

281 wire [1:0] state;

282 wire ack;

283

284 GBZ80Core core(

285 .clk(clk),

286 .bus0address(addr[0]),

287 .bus0data(data[0]),

288 .bus0wr(wr[0]),

289 .bus0rd(rd[0]),

290 .bus1address(addr[1]),

291 .bus1data(data[1]),

292 .bus1wr(wr[1]),

293 .bus1rd(rd[1]),

294 .irq(irq),

295 .irqack(ack),

296 .jaddr(jaddr),

297 .state(state));

298

299 BootstrapROM brom(

300 .address(addr[1]),

301 .data(data[1]),

302 .clk(clk),

303 .wr(wr[1]),

304 .rd(rd[1]));

305

306 `ifdef isim

307 SimROM rom(

308 .address(addr[0]),

309 .data(data[0]),

310 .clk(clk),

311 .wr(wr[0]),

312 .rd(rd[0]));

313 `else

314 CellularRAM cellram(

315 .address(addr[0]),

316 .data(data[0]),

317 .clk(clk),

318 .wr(wr[0]),

319 .rd(rd[0]),

320 .cr_nADV(cr_nADV),

321 .cr_nCE(cr_nCE),

322 .cr_nOE(cr_nOE),

323 .cr_nWE(cr_nWE),

324 .cr_CRE(cr_CRE),

325 .cr_nLB(cr_nLB),

326 .cr_nUB(cr_nUB),

327 .cr_CLK(cr_CLK),

328 .cr_A(cr_A),

329 .cr_DQ(cr_DQ),

330 .st_nCE(st_nCE),

331 .st_nRST(st_nRST));

332 `endif

333

334 wire lcdhs, lcdvs, lcdclk;

335 wire [2:0] lcdr, lcdg;

336 wire [1:0] lcdb;

337

338 LCDC lcdc(

339 .clk(clk),

340 .addr(addr[0]),

341 .data(data[0]),

342 .wr(wr[0]),

343 .rd(rd[0]),

344 .lcdcirq(lcdcirq),

345 .vblankirq(vblankirq),

346 .lcdclk(lcdclk),

347 .lcdhs(lcdhs),

348 .lcdvs(lcdvs),

349 .lcdr(lcdr),

350 .lcdg(lcdg),

351 .lcdb(lcdb));

352

353 Framebuffer fb(

354 .lcdclk(lcdclk),

355 .lcdhs(lcdhs),

356 .lcdvs(lcdvs),

357 .lcdr(lcdr),

358 .lcdg(lcdg),

359 .lcdb(lcdb),

360 .vgaclk(vgaclk),

361 .vgahs(hs),

362 .vgavs(vs),

363 .vgar(r),

364 .vgag(g),

365 .vgab(b));

366

367 wire [7:0] sleds;

368 `ifdef isim

369 assign leds = sleds;

370 `else

371 assign leds = sleds | ps2buttons;

372 `endif

373 Switches sw(

374 .clk(clk),

375 .address(addr[0]),

376 .data(data[0]),

377 .wr(wr[0]),

378 .rd(rd[0]),

379 .ledout(sleds),

380 .switches(switches)

381 );

382

383 `ifdef isim

384 `else

385 PS2Button ps2(

386 .clk(clk),

387 .inclk(ps2c),

388 .indata(ps2d),

389 .buttons(ps2buttons)

390 );

391 `endif

392

393 Buttons ass(

394 .core_clk(clk),

395 .addr(addr[0]),

396 .data(data[0]),

397 .wr(wr[0]),

398 .rd(rd[0]),

399 .int(btnirq),

400 `ifdef isim

401 .buttons(switches)

402 `else

403 .buttons(ps2buttons)

404 `endif

405 );

406

407 AddrMon amon(

408 .clk(clk),

409 .addr(addr[0]),

410 .digit(digits),

411 .out(seven),

412 .freeze(buttons[0]),

413 .periods(

414 (state == 2'b00) ? 4'b0010 :

415 (state == 2'b01) ? 4'b0001 :

416 (state == 2'b10) ? 4'b1000 :

417 4'b0100) );

418

419 UART nouart ( /* no u */

420 .clk(clk),

421 .addr(addr[0]),

422 .data(data[0]),

423 .wr(wr[0]),

424 .rd(rd[0]),

425 .serial(serio),

426 .serialrx(serin)

427 );

428

429 InternalRAM ram(

430 .clk(clk),

431 .address(addr[0]),

432 .data(data[0]),

433 .wr(wr[0]),

434 .rd(rd[0])

435 );

436

437 MiniRAM mram(

438 .clk(clk),

439 .address(addr[1]),

440 .data(data[1]),

441 .wr(wr[1]),

442 .rd(rd[1])

443 );

444

445 Timer tmr(

446 .clk(clk),

447 .addr(addr[0]),

448 .data(data[0]),

449 .wr(wr[0]),

450 .rd(rd[0]),

451 .irq(tmrirq)

452 );

453

454 Interrupt intr(

455 .clk(clk),

456 .addr(addr[0]),

457 .data(data[0]),

458 .wr(wr[0]),

459 .rd(rd[0]),

460 .vblank(vblankirq),

461 .lcdc(lcdcirq),

462 .tovf(tmrirq),

463 .serial(1'b0),

464 .buttons(btnirq),

465 .master(irq),

466 .ack(ack),

467 .jaddr(jaddr));

468

469 Soundcore sound(

470 .core_clk(clk),

471 .addr(addr[0]),

472 .data(data[0]),

473 .rd(rd[0]),

474 .wr(wr[0]),

475 .snd_data_l(soundl),

476 .snd_data_r(soundr));

477

478 `ifdef isim

479 `else

480 Ethernet eth(

481 .clk(clk),

482 .wr(wr[0]),

483 .rd(rd[0]),

484 .addr(addr[0]),

485 .data(data[0]),

486 .ethclk(ethclk),

487 .rxclk(xtalb),

488 .txp(txp),

489 .txm(txm),

490 .rxp(rxp),

491 .rxm(rxm));

492 `endif

493 endmodule