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[fpgaboy.git] / CoreTop.xst
1 set -tmpdir "xst/projnav.tmp"
2 set -xsthdpdir "xst"
3 run
4 -ifn CoreTop.prj
5 -ifmt mixed
6 -ofn CoreTop
7 -ofmt NGC
8 -p xc3s500e-5-fg320
9 -top CoreTop
10 -opt_mode Speed
11 -opt_level 1
12 -iuc NO
13 -lso CoreTop.lso
14 -keep_hierarchy NO
15 -netlist_hierarchy as_optimized
16 -rtlview Yes
17 -glob_opt AllClockNets
18 -read_cores YES
19 -write_timing_constraints NO
20 -cross_clock_analysis NO
21 -hierarchy_separator /
22 -bus_delimiter <>
23 -case maintain
24 -slice_utilization_ratio 100
25 -bram_utilization_ratio 100
26 -verilog2001 YES
27 -fsm_extract YES -fsm_encoding Auto
28 -safe_implementation No
29 -fsm_style lut
30 -ram_extract Yes
31 -ram_style Auto
32 -rom_extract Yes
33 -mux_style Auto
34 -decoder_extract YES
35 -priority_extract YES
36 -shreg_extract YES
37 -shift_extract YES
38 -xor_collapse YES
39 -rom_style Auto
40 -auto_bram_packing NO
41 -mux_extract YES
42 -resource_sharing YES
43 -async_to_sync NO
44 -mult_style auto
45 -iobuf YES
46 -max_fanout 500
47 -bufg 24
48 -register_duplication YES
49 -register_balancing No
50 -slice_packing YES
51 -optimize_primitives NO
52 -use_clock_enable Yes
53 -use_sync_set Yes
54 -use_sync_reset Yes
55 -iob auto
56 -equivalent_register_removal YES
57 -slice_utilization_ratio_maxmargin 5
Partial Nintendo GameBoy / GBZ80 implementation on a Xilinx FPGA
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