Readd .keep
[fpgaboy.git] / System.v
1
2 `timescale 1ns / 1ps
3 module ROM(
4         input [15:0] address,
5         inout [7:0] data,
6         input clk,
7         input wr, rd);
8
9         reg [7:0] rom [1023:0];
10         initial $readmemh("rom.hex", rom);
11
12         wire decode = address[15:13] == 0;
13         wire [7:0] odata = rom[address[10:0]];
14         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
15         //assign data = rd ? odata : 8'bzzzzzzzz;
16 endmodule
17
18 module InternalRAM(
19         input [15:0] address,
20         inout [7:0] data,
21         input clk,
22         input wr, rd);
23         
24         // synthesis attribute ram_style of ram is block
25         reg [7:0] ram [8191:0];
26         
27         wire decode = address[15:13] == 3'b110;
28         reg [7:0] odata;
29         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
30         
31         always @(negedge clk)
32         begin
33                 if (decode)     // This has to go this way. The only way XST knows how to do
34                 begin                           // block ram is chip select, write enable, and always
35                         if (wr)         // reading. "else if rd" does not cut it ...
36                                 ram[address[12:0]] <= data;
37                         odata <= ram[address[12:0]];
38                 end
39         end
40 endmodule
41
42 module Switches(
43         input [15:0] address,
44         inout [7:0] data,
45         input clk,
46         input wr, rd,
47         input [7:0] switches,
48         output reg [7:0] ledout = 0);
49         
50         wire decode = address == 16'hFF51;
51         reg [7:0] odata;
52         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
53         
54         always @(negedge clk)
55         begin
56                 if (decode && rd)
57                         odata <= switches;
58                 else if (decode && wr)
59                         ledout <= data;
60         end
61 endmodule
62
63 module CoreTop(
64         input xtal,
65         input [7:0] switches,
66         input [3:0] buttons,
67         output wire [7:0] leds,
68         output serio,
69         output wire [3:0] digits,
70         output wire [7:0] seven,
71         output wire hs, vs,
72         output wire [2:0] r, g,
73         output wire [1:0] b);
74         
75         wire xtalb, clk, vgaclk;
76         IBUFG iclkbuf(.O(xtalb), .I(xtal));
77         CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
78         pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
79         
80         wire [15:0] addr;       
81         wire [7:0] data;
82         wire wr, rd;
83         
84         wire irq, tmrirq, lcdcirq, vblankirq;
85         wire [7:0] jaddr;
86         wire [1:0] state;
87         
88         GBZ80Core core(
89                 .clk(clk),
90                 .busaddress(addr),
91                 .busdata(data),
92                 .buswr(wr),
93                 .busrd(rd),
94                 .irq(irq),
95                 .jaddr(jaddr),
96                 .state(state));
97         
98         ROM rom(
99                 .address(addr),
100                 .data(data),
101                 .clk(clk),
102                 .wr(wr),
103                 .rd(rd));
104         
105         wire lcdhs, lcdvs, lcdclk;
106         wire [2:0] lcdr, lcdg;
107         wire [1:0] lcdb;
108         
109         LCDC lcdc(
110                 .addr(addr),
111                 .data(data),
112                 .clk(clk),
113                 .wr(wr),
114                 .rd(rd),
115                 .lcdcirq(lcdcirq),
116                 .vblankirq(vblankirq),
117                 .lcdclk(lcdclk),
118                 .lcdhs(lcdhs),
119                 .lcdvs(lcdvs),
120                 .lcdr(lcdr),
121                 .lcdg(lcdg),
122                 .lcdb(lcdb));
123         
124         Framebuffer fb(
125                 .lcdclk(lcdclk),
126                 .lcdhs(lcdhs),
127                 .lcdvs(lcdvs),
128                 .lcdr(lcdr),
129                 .lcdg(lcdg),
130                 .lcdb(lcdb),
131                 .vgaclk(vgaclk),
132                 .vgahs(hs),
133                 .vgavs(vs),
134                 .vgar(r),
135                 .vgag(g),
136                 .vgab(b));
137         
138         AddrMon amon(
139                 .addr(addr), 
140                 .clk(clk), 
141                 .digit(digits), 
142                 .out(seven),
143                 .freeze(buttons[0]),
144                 .periods(
145                         (state == 2'b00) ? 4'b0010 :
146                         (state == 2'b01) ? 4'b0001 :
147                         (state == 2'b10) ? 4'b1000 :
148                                            4'b0100) );
149          
150         Switches sw(
151                 .address(addr),
152                 .data(data),
153                 .clk(clk),
154                 .wr(wr),
155                 .rd(rd),
156                 .ledout(leds),
157                 .switches(switches)
158                 );
159
160         UART nouart (   /* no u */
161                 .clk(clk), 
162                 .wr(wr), 
163                 .rd(rd), 
164                 .addr(addr), 
165                 .data(data), 
166                 .serial(serio)
167                 );
168
169         InternalRAM ram(
170                 .address(addr),
171                 .data(data),
172                 .clk(clk),
173                 .wr(wr),
174                 .rd(rd)
175                 );
176
177         Timer tmr(
178                 .clk(clk),
179                 .wr(wr),
180                 .rd(rd),
181                 .addr(addr),
182                 .data(data),
183                 .irq(tmrirq)
184                 );
185         
186         Interrupt intr(
187                 .clk(clk),
188                 .rd(rd),
189                 .wr(wr),
190                 .addr(addr),
191                 .data(data),
192                 .vblank(vblankirq),
193                 .lcdc(lcdcirq),
194                 .tovf(tmrirq),
195                 .serial(0),
196                 .buttons(0),
197                 .master(irq),
198                 .jaddr(jaddr));
199 endmodule
200
201 module TestBench();
202         reg clk = 1;
203         wire [15:0] addr;
204         wire [7:0] data;
205         wire wr, rd;
206         
207         wire irq, tmrirq;
208         wire [7:0] jaddr;
209         
210         wire [7:0] leds;
211         wire [7:0] switches;
212         
213         always #62 clk <= ~clk;
214         GBZ80Core core(
215                 .clk(clk),
216                 .busaddress(addr),
217                 .busdata(data),
218                 .buswr(wr),
219                 .busrd(rd),
220                 .irq(irq),
221                 .jaddr(jaddr));
222         
223         ROM rom(
224                 .clk(clk),
225                 .address(addr),
226                 .data(data),
227                 .wr(wr),
228                 .rd(rd));
229         
230         InternalRAM ram(
231                 .address(addr),
232                 .data(data),
233                 .clk(clk),
234                 .wr(wr),
235                 .rd(rd));
236
237         wire serio;
238         UART uart(
239                 .addr(addr),
240                 .data(data),
241                 .clk(clk),
242                 .wr(wr),
243                 .rd(rd),
244                 .serial(serio));
245         
246         Timer tmr(
247                 .clk(clk),
248                 .wr(wr),
249                 .rd(rd),
250                 .addr(addr),
251                 .data(data),
252                 .irq(tmrirq));
253         
254         Interrupt intr(
255                 .clk(clk),
256                 .rd(rd),
257                 .wr(wr),
258                 .addr(addr),
259                 .data(data),
260                 .vblank(0),
261                 .lcdc(0),
262                 .tovf(tmrirq),
263                 .serial(0),
264                 .buttons(0),
265                 .master(irq),
266                 .jaddr(jaddr));
267         
268         Switches sw(
269                 .clk(clk),
270                 .address(addr),
271                 .data(data),
272                 .wr(wr),
273                 .rd(rd),
274                 .switches(switches),
275                 .ledout(leds));
276 endmodule
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