System.v

   1
   2 `timescale 1ns / 1ps
   3 module ROM(
   4         input [15:0] address,
   5         inout [7:0] data,
   6         input clk,
   7         input wr, rd);
   8
   9         reg [7:0] rom [2047:0];
  10         initial $readmemh("rom.hex", rom);
  11
  12         wire decode = address[15:13] == 0;
  13         wire [7:0] odata = rom[address[11:0]];
  14         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
  15         //assign data = rd ? odata : 8'bzzzzzzzz;
  16 endmodule
  17
  18 module InternalRAM(
  19         input [15:0] address,
  20         inout [7:0] data,
  21         input clk,
  22         input wr, rd);
  23
  24         // synthesis attribute ram_style of reg is block
  25         reg [7:0] ram [8191:0];
  26
  27         wire decode = address[15:13] == 3'b110;
  28         reg [7:0] odata;
  29         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
  30
  31         always @(negedge clk)
  32         begin
  33                 if (decode)     // This has to go this way. The only way XST knows how to do
  34                 begin                           // block ram is chip select, write enable, and always
  35                         if (wr)         // reading. "else if rd" does not cut it ...
  36                                 ram[address[12:0]] <= data;
  37                         odata <= ram[address[12:0]];
  38                 end
  39         end
  40 endmodule
  41
  42 module Switches(
  43         input [15:0] address,
  44         inout [7:0] data,
  45         input clk,
  46         input wr, rd,
  47         input [7:0] switches,
  48         output reg [7:0] ledout = 0);
  49
  50         wire decode = address == 16'hFF51;
  51         reg [7:0] odata;
  52         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
  53
  54         always @(negedge clk)
  55         begin
  56                 if (decode && rd)
  57                         odata <= switches;
  58                 else if (decode && wr)
  59                         ledout <= data;
  60         end
  61 endmodule
  62
  63 module CoreTop(
  64         input xtal,
  65         input [7:0] switches,
  66         input [3:0] buttons,
  67         output wire [7:0] leds,
  68         output serio,
  69         output wire [3:0] digits,
  70         output wire [7:0] seven);
  71
  72         wire clk;
  73         CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
  74
  75         wire [15:0] addr;
  76         wire [7:0] data;
  77         wire wr, rd;
  78
  79         wire irq, tmrirq;
  80         wire [7:0] jaddr;
  81         wire [1:0] state;
  82
  83         GBZ80Core core(
  84                 .clk(clk),
  85                 .busaddress(addr),
  86                 .busdata(data),
  87                 .buswr(wr),
  88                 .busrd(rd),
  89                 .irq(irq),
  90                 .jaddr(jaddr),
  91                 .state(state));
  92
  93         ROM rom(
  94                 .address(addr),
  95                 .data(data),
  96                 .clk(clk),
  97                 .wr(wr),
  98                 .rd(rd));
  99
 100         AddrMon amon(
 101                 .addr(addr),
 102                 .clk(clk),
 103                 .digit(digits),
 104                 .out(seven),
 105                 .freeze(buttons[0]),
 106                 .periods(
 107                         (state == 2'b00) ? 4'b0010 :
 108                         (state == 2'b01) ? 4'b0001 :
 109                         (state == 2'b10) ? 4'b1000 :
 110                                            4'b0100) );
 111
 112         Switches sw(
 113                 .address(addr),
 114                 .data(data),
 115                 .clk(clk),
 116                 .wr(wr),
 117                 .rd(rd),
 118                 .ledout(leds),
 119                 .switches(switches)
 120                 );
 121
 122         UART nouart (   /* no u */
 123                 .clk(clk),
 124                 .wr(wr),
 125                 .rd(rd),
 126                 .addr(addr),
 127                 .data(data),
 128                 .serial(serio)
 129                 );
 130
 131         InternalRAM ram(
 132                 .address(addr),
 133                 .data(data),
 134                 .clk(clk),
 135                 .wr(wr),
 136                 .rd(rd)
 137                 );
 138
 139         Timer tmr(
 140                 .clk(clk),
 141                 .wr(wr),
 142                 .rd(rd),
 143                 .addr(addr),
 144                 .data(data),
 145                 .irq(tmrirq)
 146                 );
 147
 148         Interrupt intr(
 149                 .clk(clk),
 150                 .rd(rd),
 151                 .wr(wr),
 152                 .addr(addr),
 153                 .data(data),
 154                 .vblank(0),
 155                 .lcdc(0),
 156                 .tovf(tmrirq),
 157                 .serial(0),
 158                 .buttons(0),
 159                 .master(irq),
 160                 .jaddr(jaddr));
 161 endmodule
 162
 163 module TestBench();
 164         reg clk = 1;
 165         wire [15:0] addr;
 166         wire [7:0] data;
 167         wire wr, rd;
 168
 169         wire irq, tmrirq;
 170         wire [7:0] jaddr;
 171
 172         wire [7:0] leds;
 173         wire [7:0] switches;
 174
 175         always #62 clk <= ~clk;
 176         GBZ80Core core(
 177                 .clk(clk),
 178                 .busaddress(addr),
 179                 .busdata(data),
 180                 .buswr(wr),
 181                 .busrd(rd),
 182                 .irq(irq),
 183                 .jaddr(jaddr));
 184
 185         ROM rom(
 186                 .clk(clk),
 187                 .address(addr),
 188                 .data(data),
 189                 .wr(wr),
 190                 .rd(rd));
 191
 192         InternalRAM ram(
 193                 .address(addr),
 194                 .data(data),
 195                 .clk(clk),
 196                 .wr(wr),
 197                 .rd(rd));
 198
 199         wire serio;
 200         UART uart(
 201                 .addr(addr),
 202                 .data(data),
 203                 .clk(clk),
 204                 .wr(wr),
 205                 .rd(rd),
 206                 .serial(serio));
 207
 208         Timer tmr(
 209                 .clk(clk),
 210                 .wr(wr),
 211                 .rd(rd),
 212                 .addr(addr),
 213                 .data(data),
 214                 .irq(tmrirq));
 215
 216         Interrupt intr(
 217                 .clk(clk),
 218                 .rd(rd),
 219                 .wr(wr),
 220                 .addr(addr),
 221                 .data(data),
 222                 .vblank(0),
 223                 .lcdc(0),
 224                 .tovf(tmrirq),
 225                 .serial(0),
 226                 .buttons(0),
 227                 .master(irq),
 228                 .jaddr(jaddr));
 229
 230         Switches sw(
 231                 .clk(clk),
 232                 .address(addr),
 233                 .data(data),
 234                 .wr(wr),
 235                 .rd(rd),
 236                 .switches(switches),
 237                 .ledout(leds));
 238 endmodule