f89b2a6538ade01a2052737eb15d59adfa3a1d5a
[fpgaboy.git] / System.v
1
2 `timescale 1ns / 1ps
3 module SimROM(
4         input [15:0] address,
5         inout [7:0] data,
6         input clk,
7         input wr, rd);
8
9         reg rdlatch = 0;
10         reg [7:0] odata;
11
12         reg [7:0] rom [32767:0];
13         initial $readmemh("rom.hex", rom);
14
15         wire decode = address[15:13] == 0;
16         always @(posedge clk) begin
17                 rdlatch <= rd && decode;
18                 odata <= rom[address[10:0]];
19         end
20         assign data = rdlatch ? odata : 8'bzzzzzzzz;
21 endmodule
22
23 module BootstrapROM(
24         input [15:0] address,
25         inout [7:0] data,
26         input clk,
27         input wr, rd);
28
29         reg rdlatch = 0;
30         reg [7:0] addrlatch = 0;
31         reg romno = 0, romnotmp = 0;
32         reg [7:0] brom0 [255:0];
33         reg [7:0] brom1 [255:0];
34         
35         initial $readmemh("fpgaboot.hex", brom0);
36         initial $readmemh("gbboot.hex", brom1);
37         
38 `ifdef isim
39         initial romno <= 1;
40 `endif
41
42         wire decode = address[15:8] == 0;
43         wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];
44         always @(posedge clk) begin
45                 rdlatch <= rd && decode;
46                 addrlatch <= address[7:0];
47                 if (wr && decode) romnotmp <= data[0];
48                 if (rd && address == 16'h0000) romno <= romnotmp;       /* Latch when the program restarts. */
49         end
50         assign data = rdlatch ? odata : 8'bzzzzzzzz;
51 endmodule
52
53 module MiniRAM(
54         input [15:0] address,
55         inout [7:0] data,
56         input clk,
57         input wr, rd);
58         
59         reg [7:0] ram [127:0];
60         
61         wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
62         reg rdlatch = 0;
63         reg [7:0] odata;
64         assign data = rdlatch ? odata : 8'bzzzzzzzz;
65         
66         always @(posedge clk)
67         begin
68                 rdlatch <= rd && decode;
69                 if (decode)             // This has to go this way. The only way XST knows how to do
70                 begin                   // block ram is chip select, write enable, and always
71                         if (wr)         // reading. "else if rd" does not cut it ...
72                                 ram[address[6:0]] <= data;
73                         odata <= ram[address[6:0]];
74                 end
75         end
76 endmodule
77
78 module CellularRAM(
79         input clk,
80         input [15:0] address,
81         inout [7:0] data,
82         input wr, rd,
83         output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
84         output wire st_nCE, st_nRST,
85         output wire [22:0] cr_A,
86         inout [15:0] cr_DQ);
87         
88         parameter ADDR_PROGADDRH = 16'hFF60;
89         parameter ADDR_PROGADDRM = 16'hFF61;
90         parameter ADDR_PROGADDRL = 16'hFF62;
91         parameter ADDR_PROGDATA = 16'hFF63;
92         parameter ADDR_PROGFLASH = 16'hFF65;
93         parameter ADDR_MBC = 16'hFF64;
94         
95         reg rdlatch = 0, wrlatch = 0;
96         reg [15:0] addrlatch = 0;
97         reg [7:0] datalatch = 0;
98         
99         reg [7:0] progaddrh, progaddrm, progaddrl;
100         
101         reg [22:0] progaddr;
102         
103         reg [7:0] mbc_emul = 8'b00000101;       // High bit is whether we're poking flash
104                                                 // low 7 bits are the MBC that we are emulating
105         
106         assign cr_nADV = 0;     /* Addresses are always valid! :D */
107         assign cr_nCE = ~(addrlatch != ADDR_PROGFLASH); /* The chip is enabled */
108         assign cr_nLB = 0;      /* Lower byte is enabled */
109         assign cr_nUB = 0;      /* Upper byte is enabled */
110         assign cr_CRE = 0;      /* Data writes, not config */
111         assign cr_CLK = 0;      /* Clock? I think not! */
112         
113         assign st_nRST = 1;     /* Keep the strataflash out of reset. */
114         assign st_nCE = ~(addrlatch == ADDR_PROGFLASH);
115         
116         wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH);
117         
118         reg [3:0] rambank = 0;
119         reg [8:0] rombank = 1;
120         
121         assign cr_nOE = decode ? ~rdlatch : 1;
122         assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH) || (mbc_emul[6:0] == 0) || (addrlatch[15:13] == 3'b101))) ? ~wrlatch : 1;
123         
124         assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
125         assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom, home bank */ {9'b0,addrlatch[13:0]} :
126                         (addrlatch[15:14] == 2'b01) ? /* extrom, paged bank */ {rombank, addrlatch[13:0]} :
127                         (addrlatch[15:13] == 3'b101) ? /* extram */ {1'b1, 5'b0, rambank, addrlatch[12:0]} :
128                         ((addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH)) ? progaddr :
129                         23'b0;
130         
131         always @(posedge clk) begin
132                 case (address)
133                 ADDR_PROGADDRH: if (wr) progaddrh <= data;
134                 ADDR_PROGADDRM: if (wr) progaddrm <= data;
135                 ADDR_PROGADDRL: if (wr) progaddrl <= data;
136                 ADDR_PROGDATA:  if (rd || wr) begin
137                                         progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};
138                                         {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;
139                                 end
140                 ADDR_PROGFLASH: if (rd || wr) begin
141                                         progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};
142                                         {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;
143                                 end
144                 ADDR_MBC:       begin
145                                         mbc_emul <= data;
146                                         rambank <= 0;
147                                         rombank <= 1;
148                                 end
149                 endcase
150                 
151                 if (mbc_emul[6:0] == 5) begin
152                         if ((address[15:12] == 4'h2) && wr)
153                                 rombank <= {rombank[8], data};
154                         else if ((address[15:12] == 4'h3) && wr)
155                                 rombank <= {data[0], rombank[7:0]};
156                         else if ((address[15:12] == 4'h4) && wr)
157                                 rambank <= data[3:0];
158                 end
159                 
160                 rdlatch <= rd;
161                 wrlatch <= wr;
162                 addrlatch <= address;
163                 datalatch <= data;
164         end
165         
166         assign data = (rdlatch && decode) ?
167                                 (addrlatch == ADDR_PROGADDRH) ? progaddrh :
168                                 (addrlatch == ADDR_PROGADDRM) ? progaddrm :
169                                 (addrlatch == ADDR_PROGADDRL) ? progaddrl :
170                                 cr_DQ
171                         : 8'bzzzzzzzz;
172 endmodule
173
174 module InternalRAM(
175         input [15:0] address,
176         inout [7:0] data,
177         input clk,
178         input wr, rd);
179         
180         // synthesis attribute ram_style of ram is block
181         reg [7:0] ram [8191:0];
182         
183         wire decode = (address >= 16'hC000) && (address <= 16'hFDFF);   /* This includes echo RAM. */
184         reg [7:0] odata;
185         reg rdlatch = 0;
186         assign data = rdlatch ? odata : 8'bzzzzzzzz;
187         
188         always @(posedge clk)
189         begin
190                 rdlatch <= rd && decode;
191                 if (decode)             // This has to go this way. The only way XST knows how to do
192                 begin                   // block ram is chip select, write enable, and always
193                         if (wr)         // reading. "else if rd" does not cut it ...
194                                 ram[address[12:0]] <= data;
195                         odata <= ram[address[12:0]];
196                 end
197         end
198 endmodule
199
200 module Switches(
201         input [15:0] address,
202         inout [7:0] data,
203         input clk,
204         input wr, rd,
205         input [7:0] switches,
206         output reg [7:0] ledout = 0);
207         
208         wire decode = address == 16'hFF51;
209         reg [7:0] odata;
210         reg rdlatch = 0;
211         assign data = rdlatch ? odata : 8'bzzzzzzzz;
212         
213         always @(posedge clk)
214         begin
215                 rdlatch <= rd && decode;
216                 if (decode && rd)
217                         odata <= switches;
218                 else if (decode && wr)
219                         ledout <= data;
220         end
221 endmodule
222
223 `ifdef isim
224 module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
225 endmodule
226 `endif
227
228 module CoreTop(
229 `ifdef isim
230         output reg vgaclk = 0,
231         output reg clk = 0,
232 `else
233         input xtal,
234         input [7:0] switches,
235         input [3:0] buttons,
236         output wire [7:0] leds,
237         output serio,
238         input serin,
239         output wire [3:0] digits,
240         output wire [7:0] seven,
241         output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK, st_nCE, st_nRST,
242         output wire [22:0] cr_A,
243         inout [15:0] cr_DQ,
244         input ps2c, ps2d,
245 `endif
246         output wire hs, vs,
247         output wire [2:0] r, g,
248         output wire [1:0] b,
249         output wire soundl, soundr);
250
251 `ifdef isim
252         always #62 clk <= ~clk;
253         always #100 vgaclk <= ~vgaclk;
254         
255         Dumpable dump(r,g,b,hs,vs,vgaclk);
256         
257         wire [7:0] leds;
258         wire serio;
259         wire serin = 1;
260         wire [3:0] digits;
261         wire [7:0] seven;
262         wire [7:0] switches = 8'b0;
263         wire [3:0] buttons = 4'b0;
264 `else   
265         wire xtalb, clk, vgaclk;
266         IBUFG iclkbuf(.O(xtalb), .I(xtal));
267         CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
268         pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
269         wire [7:0] ps2buttons;
270 `endif
271
272         wire [15:0] addr [1:0];
273         wire [7:0] data [1:0];
274         wire wr [1:0], rd [1:0];
275         
276         wire irq, tmrirq, lcdcirq, vblankirq, btnirq;
277         wire [7:0] jaddr;
278         wire [1:0] state;
279         wire ack;
280         
281         GBZ80Core core(
282                 .clk(clk),
283                 .bus0address(addr[0]),
284                 .bus0data(data[0]),
285                 .bus0wr(wr[0]),
286                 .bus0rd(rd[0]),
287                 .bus1address(addr[1]),
288                 .bus1data(data[1]),
289                 .bus1wr(wr[1]),
290                 .bus1rd(rd[1]),
291                 .irq(irq),
292                 .irqack(ack),
293                 .jaddr(jaddr),
294                 .state(state));
295         
296         BootstrapROM brom(
297                 .address(addr[1]),
298                 .data(data[1]),
299                 .clk(clk),
300                 .wr(wr[1]),
301                 .rd(rd[1]));
302         
303 `ifdef isim
304         SimROM rom(
305                 .address(addr[0]),
306                 .data(data[0]),
307                 .clk(clk),
308                 .wr(wr[0]),
309                 .rd(rd[0]));
310 `else
311         CellularRAM cellram(
312                 .address(addr[0]),
313                 .data(data[0]),
314                 .clk(clk),
315                 .wr(wr[0]),
316                 .rd(rd[0]),
317                 .cr_nADV(cr_nADV),
318                 .cr_nCE(cr_nCE),
319                 .cr_nOE(cr_nOE),
320                 .cr_nWE(cr_nWE),
321                 .cr_CRE(cr_CRE),
322                 .cr_nLB(cr_nLB),
323                 .cr_nUB(cr_nUB),
324                 .cr_CLK(cr_CLK),
325                 .cr_A(cr_A),
326                 .cr_DQ(cr_DQ),
327                 .st_nCE(st_nCE),
328                 .st_nRST(st_nRST));
329 `endif
330         
331         wire lcdhs, lcdvs, lcdclk;
332         wire [2:0] lcdr, lcdg;
333         wire [1:0] lcdb;
334         
335         LCDC lcdc(
336                 .clk(clk),
337                 .addr(addr[0]),
338                 .data(data[0]),
339                 .wr(wr[0]),
340                 .rd(rd[0]),
341                 .lcdcirq(lcdcirq),
342                 .vblankirq(vblankirq),
343                 .lcdclk(lcdclk),
344                 .lcdhs(lcdhs),
345                 .lcdvs(lcdvs),
346                 .lcdr(lcdr),
347                 .lcdg(lcdg),
348                 .lcdb(lcdb));
349         
350         Framebuffer fb(
351                 .lcdclk(lcdclk),
352                 .lcdhs(lcdhs),
353                 .lcdvs(lcdvs),
354                 .lcdr(lcdr),
355                 .lcdg(lcdg),
356                 .lcdb(lcdb),
357                 .vgaclk(vgaclk),
358                 .vgahs(hs),
359                 .vgavs(vs),
360                 .vgar(r),
361                 .vgag(g),
362                 .vgab(b));
363
364         wire [7:0] sleds;
365 `ifdef isim
366         assign leds = sleds;
367 `else
368         assign leds = sleds | ps2buttons;
369 `endif
370         Switches sw(
371                 .clk(clk),
372                 .address(addr[0]),
373                 .data(data[0]),
374                 .wr(wr[0]),
375                 .rd(rd[0]),
376                 .ledout(sleds),
377                 .switches(switches)
378                 );
379         
380 `ifdef isim
381 `else
382         PS2Button ps2(
383                 .clk(clk),
384                 .inclk(ps2c),
385                 .indata(ps2d),
386                 .buttons(ps2buttons)
387                 );
388 `endif
389         
390         Buttons ass(
391                 .core_clk(clk),
392                 .addr(addr[0]),
393                 .data(data[0]),
394                 .wr(wr[0]),
395                 .rd(rd[0]),
396                 .int(btnirq),
397         `ifdef isim
398                 .buttons(switches)
399         `else
400                 .buttons(ps2buttons)
401         `endif
402                 );
403
404         AddrMon amon(
405                 .clk(clk), 
406                 .addr(addr[0]),
407                 .digit(digits), 
408                 .out(seven),
409                 .freeze(buttons[0]),
410                 .periods(
411                         (state == 2'b00) ? 4'b0010 :
412                         (state == 2'b01) ? 4'b0001 :
413                         (state == 2'b10) ? 4'b1000 :
414                                            4'b0100) );
415          
416         UART nouart (   /* no u */
417                 .clk(clk),
418                 .addr(addr[0]),
419                 .data(data[0]),
420                 .wr(wr[0]),
421                 .rd(rd[0]),
422                 .serial(serio),
423                 .serialrx(serin)
424                 );
425
426         InternalRAM ram(
427                 .clk(clk),
428                 .address(addr[0]),
429                 .data(data[0]),
430                 .wr(wr[0]),
431                 .rd(rd[0])
432                 );
433         
434         MiniRAM mram(
435                 .clk(clk),
436                 .address(addr[1]),
437                 .data(data[1]),
438                 .wr(wr[1]),
439                 .rd(rd[1])
440                 );
441
442         Timer tmr(
443                 .clk(clk),
444                 .addr(addr[0]),
445                 .data(data[0]),
446                 .wr(wr[0]),
447                 .rd(rd[0]),
448                 .irq(tmrirq)
449                 );
450         
451         Interrupt intr(
452                 .clk(clk),
453                 .addr(addr[0]),
454                 .data(data[0]),
455                 .wr(wr[0]),
456                 .rd(rd[0]),
457                 .vblank(vblankirq),
458                 .lcdc(lcdcirq),
459                 .tovf(tmrirq),
460                 .serial(1'b0),
461                 .buttons(btnirq),
462                 .master(irq),
463                 .ack(ack),
464                 .jaddr(jaddr));
465         
466         Soundcore sound(
467                 .core_clk(clk),
468                 .addr(addr[0]),
469                 .data(data[0]),
470                 .rd(rd[0]),
471                 .wr(wr[0]),
472                 .snd_data_l(soundl),
473                 .snd_data_r(soundr));
474 endmodule
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