ALU8IMM
[fpgaboy.git] / GBZ80Core.v
1 `define REG_A   0
2 `define REG_B   1
3 `define REG_C   2
4 `define REG_D   3
5 `define REG_E   4
6 `define REG_F   5
7 `define REG_H   6
8 `define REG_L   7
9 `define REG_SPH 8
10 `define REG_SPL 9
11 `define REG_PCH 10
12 `define REG_PCL 11
13
14 `define _A      registers[`REG_A]
15 `define _B      registers[`REG_B]
16 `define _C      registers[`REG_C]
17 `define _D      registers[`REG_D]
18 `define _E      registers[`REG_E]
19 `define _F      registers[`REG_F]
20 `define _H      registers[`REG_H]
21 `define _L      registers[`REG_L]
22 `define _SPH    registers[`REG_SPH]
23 `define _SPL    registers[`REG_SPL]
24 `define _PCH    registers[`REG_PCH]
25 `define _PCL    registers[`REG_PCL]
26 `define _AF     {`_A, `_F}
27 `define _BC     {`_B, `_C}
28 `define _DE     {`_D, `_E}
29 `define _HL     {`_H, `_L}
30 `define _SP     {`_SPH, `_SPL}
31 `define _PC     {`_PCH, `_PCL}
32
33 `define FLAG_Z  8'b10000000
34 `define FLAG_N  8'b01000000
35 `define FLAG_H  8'b00100000
36 `define FLAG_C  8'b00010000
37
38 `define STATE_FETCH             2'h0
39 `define STATE_DECODE            2'h1
40 `define STATE_EXECUTE           2'h2
41 `define STATE_WRITEBACK         2'h3
42
43 `define INSN_LD_reg_imm8        8'b00xxx110
44 `define INSN_HALT               8'b01110110
45 `define INSN_LD_HL_reg          8'b01110xxx
46 `define INSN_LD_reg_HL          8'b01xxx110
47 `define INSN_LD_reg_reg         8'b01xxxxxx
48 `define INSN_LD_reg_imm16       8'b00xx0001
49 `define INSN_LD_SP_HL           8'b11111001
50 `define INSN_PUSH_reg           8'b11xx0101
51 `define INSN_POP_reg            8'b11xx0001
52 `define INSN_LDH_AC             8'b111x0010     // Either LDH A,(C) or LDH (C),A
53 `define INSN_LDx_AHL            8'b001xx010     // LDD/LDI A,(HL) / (HL),A
54 `define INSN_ALU8               8'b10xxxxxx     // 10 xxx yyy
55 `define INSN_ALU8IMM            8'b11xxx110
56 `define INSN_NOP                8'b00000000
57 `define INSN_RST                8'b11xxx111
58 `define INSN_RET                8'b110x1001     // 1 = RETI, 0 = RET
59 `define INSN_RETCC              8'b110xx000
60 `define INSN_CALL               8'b11001101
61 `define INSN_CALLCC             8'b110xx100     // Not that call/cc.
62 `define INSN_JP_imm             8'b11000011
63 `define INSN_JPCC_imm           8'b110xx010
64 `define INSN_ALU_A              8'b00xxx111
65 `define INSN_JP_HL              8'b11101001
66 `define INSN_JR_imm             8'b00011000
67 `define INSN_JRCC_imm           8'b001xx000
68 `define INSN_INCDEC16           8'b00xxx011
69 `define INSN_VOP_INTR           8'b11111100     // 0xFC is grabbed by the fetch if there is an interrupt pending.
70 `define INSN_DI                 8'b11110011
71 `define INSN_EI                 8'b11111011
72
73 `define INSN_cc_NZ              2'b00
74 `define INSN_cc_Z               2'b01
75 `define INSN_cc_NC              2'b10
76 `define INSN_cc_C               2'b11
77
78 `define INSN_reg_A              3'b111
79 `define INSN_reg_B              3'b000
80 `define INSN_reg_C              3'b001
81 `define INSN_reg_D              3'b010
82 `define INSN_reg_E              3'b011
83 `define INSN_reg_H              3'b100
84 `define INSN_reg_L              3'b101
85 `define INSN_reg_dHL            3'b110
86 `define INSN_reg16_BC           2'b00
87 `define INSN_reg16_DE           2'b01
88 `define INSN_reg16_HL           2'b10
89 `define INSN_reg16_SP           2'b11
90 `define INSN_stack_AF           2'b11
91 `define INSN_stack_BC           2'b00
92 `define INSN_stack_DE           2'b01
93 `define INSN_stack_HL           2'b10
94 `define INSN_alu_ADD            3'b000
95 `define INSN_alu_ADC            3'b001
96 `define INSN_alu_SUB            3'b010
97 `define INSN_alu_SBC            3'b011
98 `define INSN_alu_AND            3'b100
99 `define INSN_alu_XOR            3'b101
100 `define INSN_alu_OR             3'b110
101 `define INSN_alu_CP             3'b111          // Oh lawd, is dat some CP?
102 `define INSN_alu_RLCA           3'b000
103 `define INSN_alu_RRCA           3'b001
104 `define INSN_alu_RLA            3'b010
105 `define INSN_alu_RRA            3'b011
106 `define INSN_alu_DAA            3'b100
107 `define INSN_alu_CPL            3'b101
108 `define INSN_alu_SCF            3'b110
109 `define INSN_alu_CCF            3'b111
110
111 `define EXEC_INC_PC             `_PC <= `_PC + 1;
112 `define EXEC_NEXTADDR_PCINC     address <= `_PC + 1;
113 `define EXEC_NEWCYCLE           begin newcycle <= 1; rd <= 1; wr <= 0; end
114 `define EXEC_WRITE(ad, da)      begin address <= (ad); wdata <= (da); wr <= 1; end end
115 `define EXEC_READ(ad)           begin address <= (ad); rd <= 1; end end
116
117 module GBZ80Core(
118         input clk,
119         output reg [15:0] busaddress,   /* BUS_* is latched on STATE_FETCH. */
120         inout [7:0] busdata,
121         output reg buswr, output reg busrd,
122         input irq, input [7:0] jaddr,
123         output reg [1:0] state);
124         
125 //      reg [1:0] state;                                        /* State within this bus cycle (see STATE_*). */
126         reg [2:0] cycle;                                        /* Cycle for instructions. */
127         
128         reg [7:0] registers[11:0];
129         
130         reg [15:0] address;                             /* Address for the next bus operation. */
131         
132         reg [7:0] opcode;                               /* Opcode from the current machine cycle. */
133         
134         reg [7:0] rdata, wdata;         /* Read data from this bus cycle, or write data for the next. */
135         reg rd, wr, newcycle;
136         
137         reg [7:0] tmp, tmp2;                    /* Generic temporary regs. */
138         
139         reg [7:0] buswdata;
140         assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
141         
142         reg ie, iedelay;
143         
144         initial begin
145                 registers[ 0] <= 0;
146                 registers[ 1] <= 0;
147                 registers[ 2] <= 0;
148                 registers[ 3] <= 0;
149                 registers[ 4] <= 0;
150                 registers[ 5] <= 0;
151                 registers[ 6] <= 0;
152                 registers[ 7] <= 0;
153                 registers[ 8] <= 0;
154                 registers[ 9] <= 0;
155                 registers[10] <= 0;
156                 registers[11] <= 0;
157                 rd <= 1;
158                 wr <= 0;
159                 newcycle <= 1;
160                 state <= 0;
161                 cycle <= 0;
162                 busrd <= 0;
163                 buswr <= 0;
164                 busaddress <= 0;
165                 ie <= 0;
166                 iedelay <= 0;
167                 opcode <= 0;
168                 state <= `STATE_WRITEBACK;
169                 cycle <= 0;
170         end
171
172         always @(posedge clk)
173                 case (state)
174                 `STATE_FETCH: begin
175                         if (newcycle) begin
176                                 busaddress <= {registers[`REG_PCH], registers[`REG_PCL]};
177                                 buswr <= 0;
178                                 busrd <= 1;
179                         end else begin
180                                 busaddress <= address;
181                                 buswr <= wr;
182                                 busrd <= rd;
183                                 if (wr)
184                                         buswdata <= wdata;
185                         end
186                         state <= `STATE_DECODE;
187                 end
188                 `STATE_DECODE: begin
189                         if (newcycle) begin
190                                 if (ie && irq)
191                                         opcode <= `INSN_VOP_INTR;
192                                 else
193                                         opcode <= busdata;
194                                 rdata <= busdata;
195                                 newcycle <= 0;
196                                 cycle <= 0;
197                         end else begin
198                                 if (rd) rdata <= busdata;
199                                 cycle <= cycle + 1;
200                         end
201                         if (iedelay) begin
202                                 ie <= 1;
203                                 iedelay <= 0;
204                         end
205                         buswr <= 0;
206                         busrd <= 0;
207                         wr <= 0;
208                         rd <= 0;
209                         address <= 16'bxxxxxxxxxxxxxxxx;        // Make it obvious if something of type has happened.
210                         wdata <= 8'bxxxxxxxx;
211                         state <= `STATE_EXECUTE;
212                 end
213                 `STATE_EXECUTE: begin
214                         casex (opcode)
215                         `define EXECUTE
216                         `include "allinsns.v"
217                         `undef EXECUTE
218                         default:
219                                 $stop;
220                         endcase
221                         state <= `STATE_WRITEBACK;
222                 end
223                 `STATE_WRITEBACK: begin
224                         casex (opcode)
225                         `define WRITEBACK
226                         `include "allinsns.v"
227                         `undef WRITEBACK
228                         default:
229                                 $stop;
230                         endcase
231                         state <= `STATE_FETCH;
232                 end
233                 endcase
234 endmodule
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