Remove gated clock and hence remove S.
[fpgaboy.git] / insn_bit.v
1 `ifdef EXECUTE
2         `INSN_BIT: begin
3                 if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
4                         `EXEC_READ(`_HL)
5                 end else if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 2)) begin
6                         `EXEC_NEWCYCLE
7                 end else begin
8                         case (opcode[2:0])
9                         `INSN_reg_A:    tmp <= `_A;
10                         `INSN_reg_B:    tmp <= `_B;
11                         `INSN_reg_C:    tmp <= `_C;
12                         `INSN_reg_D:    tmp <= `_D;
13                         `INSN_reg_E:    tmp <= `_E;
14                         `INSN_reg_H:    tmp <= `_H;
15                         `INSN_reg_L:    tmp <= `_L;
16                         `INSN_reg_dHL:  tmp <= rdata;
17                         endcase
18                         if (opcode[2:0] != `INSN_reg_dHL) begin
19                                 `EXEC_NEWCYCLE
20                         end
21                 end
22         end
23 `endif
24
25 `ifdef WRITEBACK
26         `INSN_BIT: begin
27                 if ((opcode[2:0] != `INSN_reg_dHL) || (cycle == 1))
28                         `_F <= {~tmp[opcode[5:3]], 2'b01, `_F[4:0]};
29         end
30 `endif
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