System.v

   1
   2 `timescale 1ns / 1ps
   3 module ROM(
   4         input [15:0] address,
   5         inout [7:0] data,
   6         input clk,
   7         input wr, rd);
   8
   9         reg rdlatch = 0;
  10         reg [7:0] odata;
  11
  12         // synthesis attribute ram_style of rom is block
  13         reg [7:0] rom [1023:0];
  14         initial $readmemh("rom.hex", rom);
  15
  16         wire decode = address[15:13] == 0;
  17         always @(posedge clk) begin
  18                 rdlatch <= rd && decode;
  19                 odata <= rom[address[10:0]];
  20         end
  21         assign data = rdlatch ? odata : 8'bzzzzzzzz;
  22 endmodule
  23
  24 module BootstrapROM(
  25         input [15:0] address,
  26         inout [7:0] data,
  27         input clk,
  28         input wr, rd);
  29
  30         reg rdlatch = 0;
  31         reg [7:0] brom [255:0];
  32         initial $readmemh("bootstrap.hex", brom);
  33
  34         wire decode = address[15:8] == 0;
  35         wire [7:0] odata = brom[address[7:0]];
  36         always @(posedge clk)
  37                 rdlatch <= rd && decode;
  38         assign data = rdlatch ? odata : 8'bzzzzzzzz;
  39 endmodule
  40
  41 module MiniRAM(
  42         input [15:0] address,
  43         inout [7:0] data,
  44         input clk,
  45         input wr, rd);
  46
  47         reg [7:0] ram [127:0];
  48
  49         wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
  50         reg rdlatch = 0;
  51         reg [7:0] odata;
  52         assign data = rdlatch ? odata : 8'bzzzzzzzz;
  53
  54         always @(posedge clk)
  55         begin
  56                 rdlatch <= rd && decode;
  57                 if (decode)             // This has to go this way. The only way XST knows how to do
  58                 begin                   // block ram is chip select, write enable, and always
  59                         if (wr)         // reading. "else if rd" does not cut it ...
  60                                 ram[address[6:0]] <= data;
  61                         odata <= ram[address[6:0]];
  62                 end
  63         end
  64 endmodule
  65
  66 module CellularRAM(
  67         input clk,
  68         input [15:0] address,
  69         inout [7:0] data,
  70         input wr, rd,
  71         output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
  72         output wire [22:0] cr_A,
  73         inout [15:0] cr_DQ);
  74
  75         parameter ADDR_PROGADDRH = 16'hFF60;
  76         parameter ADDR_PROGADDRM = 16'hFF61;
  77         parameter ADDR_PROGADDRL = 16'hFF62;
  78         parameter ADDR_PROGDATA = 16'hFF63;
  79
  80         reg rdlatch = 0, wrlatch = 0;
  81         reg [15:0] addrlatch = 0;
  82         reg [7:0] datalatch = 0;
  83
  84         reg [7:0] progaddrh, progaddrm, progaddrl;
  85
  86         assign cr_nADV = 0;     /* Addresses are always valid! :D */
  87         assign cr_nCE = 0;      /* The chip is enabled */
  88         assign cr_nLB = 0;      /* Lower byte is enabled */
  89         assign cr_nUB = 0;      /* Upper byte is enabled */
  90         assign cr_CRE = 0;      /* Data writes, not config */
  91         assign cr_CLK = 0;      /* Clock? I think not! */
  92
  93         wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA);
  94
  95         assign cr_nOE = decode ? ~rdlatch : 1;
  96         assign cr_nWE = decode ? ~wrlatch : 1;
  97
  98         assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
  99         assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom */ {9'b0,addrlatch[13:0]} :
 100                         (addrlatch[15:13] == 3'b101) ? {1'b1, 9'b0, addrlatch[12:0]} :
 101                         (addrlatch == ADDR_PROGDATA) ? {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} :
 102                         23'b0;
 103
 104         reg [7:0] regbuf;
 105
 106         always @(posedge clk) begin
 107                 case (address)
 108                 ADDR_PROGADDRH: if (wr) progaddrh <= data;
 109                 ADDR_PROGADDRM: if (wr) progaddrm <= data;
 110                 ADDR_PROGADDRL: if (wr) progaddrl <= data;
 111                 endcase
 112                 rdlatch <= rd;
 113                 wrlatch <= wr;
 114                 addrlatch <= address;
 115                 datalatch <= data;
 116         end
 117
 118         assign data = (rdlatch && decode) ?
 119                                 (addrlatch == ADDR_PROGADDRH) ? progaddrh :
 120                                 (addrlatch == ADDR_PROGADDRM) ? progaddrm :
 121                                 (addrlatch == ADDR_PROGADDRL) ? progaddrl :
 122                                 cr_DQ
 123                         : 8'bzzzzzzzz;
 124 endmodule
 125
 126 module InternalRAM(
 127         input [15:0] address,
 128         inout [7:0] data,
 129         input clk,
 130         input wr, rd);
 131
 132         // synthesis attribute ram_style of ram is block
 133         reg [7:0] ram [8191:0];
 134
 135         wire decode = (address >= 16'hC000) && (address <= 16'hFDFF);   /* This includes echo RAM. */
 136         reg [7:0] odata;
 137         reg rdlatch = 0;
 138         assign data = rdlatch ? odata : 8'bzzzzzzzz;
 139
 140         always @(posedge clk)
 141         begin
 142                 rdlatch <= rd && decode;
 143                 if (decode)             // This has to go this way. The only way XST knows how to do
 144                 begin                   // block ram is chip select, write enable, and always
 145                         if (wr)         // reading. "else if rd" does not cut it ...
 146                                 ram[address[12:0]] <= data;
 147                         odata <= ram[address[12:0]];
 148                 end
 149         end
 150 endmodule
 151
 152 module Switches(
 153         input [15:0] address,
 154         inout [7:0] data,
 155         input clk,
 156         input wr, rd,
 157         input [7:0] switches,
 158         output reg [7:0] ledout = 0);
 159
 160         wire decode = address == 16'hFF51;
 161         reg [7:0] odata;
 162         reg rdlatch = 0;
 163         assign data = rdlatch ? odata : 8'bzzzzzzzz;
 164
 165         always @(posedge clk)
 166         begin
 167                 rdlatch <= rd && decode;
 168                 if (decode && rd)
 169                         odata <= switches;
 170                 else if (decode && wr)
 171                         ledout <= data;
 172         end
 173 endmodule
 174
 175 `ifdef isim
 176 module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
 177 endmodule
 178 `endif
 179
 180 module CoreTop(
 181 `ifdef isim
 182         output reg vgaclk = 0,
 183         output reg clk = 0,
 184 `else
 185         input xtal,
 186         input [7:0] switches,
 187         input [3:0] buttons,
 188         output wire [7:0] leds,
 189         output serio,
 190         output wire [3:0] digits,
 191         output wire [7:0] seven,
 192         output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
 193         output wire [22:0] cr_A,
 194         inout [15:0] cr_DQ,
 195 `endif
 196         output wire hs, vs,
 197         output wire [2:0] r, g,
 198         output wire [1:0] b,
 199         output wire soundl, soundr);
 200
 201 `ifdef isim
 202         always #62 clk <= ~clk;
 203         always #100 vgaclk <= ~vgaclk;
 204
 205         Dumpable dump(r,g,b,hs,vs,vgaclk);
 206
 207         wire [7:0] leds;
 208         wire serio;
 209         wire [3:0] digits;
 210         wire [7:0] seven;
 211         wire [7:0] switches = 8'b0;
 212         wire [3:0] buttons = 4'b0;
 213 `else
 214         wire xtalb, clk, vgaclk;
 215         IBUFG iclkbuf(.O(xtalb), .I(xtal));
 216         CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
 217         pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
 218 `endif
 219
 220         wire [15:0] addr [1:0];
 221         wire [7:0] data [1:0];
 222         wire wr [1:0], rd [1:0];
 223
 224         wire irq, tmrirq, lcdcirq, vblankirq;
 225         wire [7:0] jaddr;
 226         wire [1:0] state;
 227
 228         GBZ80Core core(
 229                 .clk(clk),
 230                 .bus0address(addr[0]),
 231                 .bus0data(data[0]),
 232                 .bus0wr(wr[0]),
 233                 .bus0rd(rd[0]),
 234                 .bus1address(addr[1]),
 235                 .bus1data(data[1]),
 236                 .bus1wr(wr[1]),
 237                 .bus1rd(rd[1]),
 238                 .irq(irq),
 239                 .jaddr(jaddr),
 240                 .state(state));
 241
 242         BootstrapROM brom(
 243                 .address(addr[1]),
 244                 .data(data[1]),
 245                 .clk(clk),
 246                 .wr(wr[1]),
 247                 .rd(rd[1]));
 248
 249 `ifdef isim
 250         ROM rom(
 251                 .address(addr[0]),
 252                 .data(data[0]),
 253                 .clk(clk),
 254                 .wr(wr[0]),
 255                 .rd(rd[0]));
 256 `else
 257         CellularRAM cellram(
 258                 .address(addr[0]),
 259                 .data(data[0]),
 260                 .clk(clk),
 261                 .wr(wr[0]),
 262                 .rd(rd[0])
 263                 .cr_nADV(cr_nADV),
 264                 .cr_nCE(cr_nCE),
 265                 .cr_nOE(cr_nOE),
 266                 .cr_nWR(cr_nWE),
 267                 .cr_CRE(cr_CRE),
 268                 .cr_nLB(cr_nLB),
 269                 .cr_nUB(cr_nUB),
 270                 .cr_CLK(cr_CLK),
 271                 .cr_A(cr_A),
 272                 .cr_DQ(cr_DQ));
 273 `endif
 274
 275         wire lcdhs, lcdvs, lcdclk;
 276         wire [2:0] lcdr, lcdg;
 277         wire [1:0] lcdb;
 278
 279         LCDC lcdc(
 280                 .clk(clk),
 281                 .addr(addr[0]),
 282                 .data(data[0]),
 283                 .wr(wr[0]),
 284                 .rd(rd[0]),
 285                 .lcdcirq(lcdcirq),
 286                 .vblankirq(vblankirq),
 287                 .lcdclk(lcdclk),
 288                 .lcdhs(lcdhs),
 289                 .lcdvs(lcdvs),
 290                 .lcdr(lcdr),
 291                 .lcdg(lcdg),
 292                 .lcdb(lcdb));
 293
 294         Framebuffer fb(
 295                 .lcdclk(lcdclk),
 296                 .lcdhs(lcdhs),
 297                 .lcdvs(lcdvs),
 298                 .lcdr(lcdr),
 299                 .lcdg(lcdg),
 300                 .lcdb(lcdb),
 301                 .vgaclk(vgaclk),
 302                 .vgahs(hs),
 303                 .vgavs(vs),
 304                 .vgar(r),
 305                 .vgag(g),
 306                 .vgab(b));
 307
 308         AddrMon amon(
 309                 .clk(clk),
 310                 .addr(addr[0]),
 311                 .digit(digits),
 312                 .out(seven),
 313                 .freeze(buttons[0]),
 314                 .periods(
 315                         (state == 2'b00) ? 4'b0010 :
 316                         (state == 2'b01) ? 4'b0001 :
 317                         (state == 2'b10) ? 4'b1000 :
 318                                            4'b0100) );
 319
 320         Switches sw(
 321                 .clk(clk),
 322                 .address(addr[0]),
 323                 .data(data[0]),
 324                 .wr(wr[0]),
 325                 .rd(rd[0]),
 326                 .ledout(leds),
 327                 .switches(switches)
 328                 );
 329
 330         UART nouart (   /* no u */
 331                 .clk(clk),
 332                 .addr(addr[0]),
 333                 .data(data[0]),
 334                 .wr(wr[0]),
 335                 .rd(rd[0]),
 336                 .serial(serio)
 337                 );
 338
 339         InternalRAM ram(
 340                 .clk(clk),
 341                 .address(addr[0]),
 342                 .data(data[0]),
 343                 .wr(wr[0]),
 344                 .rd(rd[0])
 345                 );
 346
 347         MiniRAM mram(
 348                 .clk(clk),
 349                 .address(addr[1]),
 350                 .data(data[1]),
 351                 .wr(wr[1]),
 352                 .rd(rd[1])
 353                 );
 354
 355         Timer tmr(
 356                 .clk(clk),
 357                 .addr(addr[0]),
 358                 .data(data[0]),
 359                 .wr(wr[0]),
 360                 .rd(rd[0]),
 361                 .irq(tmrirq)
 362                 );
 363
 364         Interrupt intr(
 365                 .clk(clk),
 366                 .addr(addr[0]),
 367                 .data(data[0]),
 368                 .wr(wr[0]),
 369                 .rd(rd[0]),
 370                 .vblank(vblankirq),
 371                 .lcdc(lcdcirq),
 372                 .tovf(tmrirq),
 373                 .serial(1'b0),
 374                 .buttons(1'b0),
 375                 .master(irq),
 376                 .jaddr(jaddr));
 377
 378         Soundcore sound(
 379                 .core_clk(clk),
 380                 .addr(addr[0]),
 381                 .data(data[0]),
 382                 .rd(rd[0]),
 383                 .wr(wr[0]),
 384                 .snd_data_l(soundl),
 385                 .snd_data_r(soundr));
 386 endmodule