]> Joshua Wise's Git repositories - fpgaboy.git/blob - core/insn_alu_a.v
Merge branch 'master' of lu@anyus.res.cmu.edu:/storage/fpga/FPGABoy
[fpgaboy.git] / core / insn_alu_a.v
1 `define INSN_alu_RLCA           3'b000
2 `define INSN_alu_RRCA           3'b001
3 `define INSN_alu_RLA            3'b010
4 `define INSN_alu_RRA            3'b011
5 `define INSN_alu_DAA            3'b100
6 `define INSN_alu_CPL            3'b101
7 `define INSN_alu_SCF            3'b110
8 `define INSN_alu_CCF            3'b111
9
10 `define INSN_ALU_A              9'b000xxx111
11
12 `ifdef EXECUTE
13         `INSN_ALU_A: begin
14                 `EXEC_NEWCYCLE
15                 `EXEC_INC_PC
16         end
17 `endif
18
19 `ifdef WRITEBACK
20         `INSN_ALU_A: begin
21                 case(opcode[5:3])
22                 `INSN_alu_RLCA: begin
23                         `_A <= {`_A[6:0],`_A[7]};
24                         `_F <= {`_F[7:5],`_A[7],`_F[3:0]};
25                 end
26                 `INSN_alu_RRCA: begin
27                         `_A <= {`_A[0],`_A[7:1]};
28                         `_F <= {`_F[7:5],`_A[0],`_F[3:0]};
29                 end
30                 `INSN_alu_RLA: begin
31                         `_A <= {`_A[6:0],`_F[4]};
32                         `_F <= {`_F[7:5],`_A[7],`_F[3:0]};
33                 end
34                 `INSN_alu_RRA: begin
35                         `_A <= {`_A[4],`_A[7:1]};
36                         `_F <= {`_F[7:5],`_A[0],`_F[3:0]};
37                 end
38                 `INSN_alu_CPL: begin
39                         `_A <= ~`_A;
40                         `_F <= {`_F[7],1'b1,1'b1,`_F[4:0]};
41                 end
42                 `INSN_alu_SCF: begin
43                         `_F <= {`_F[7:5],1'b1,`_F[3:0]};
44                 end
45                 `INSN_alu_CCF: begin
46                         `_F <= {`_F[7:5],~`_F[4],`_F[3:0]};
47                 end
48                 endcase
49         end
50 `endif
This page took 0.027062 seconds and 4 git commands to generate.