5 output wire [7:0] buttons
8 reg [3:0] bitcount = 0;
10 reg keyarrow = 0, keyup = 0, parity = 0;
11 reg key_a = 0,key_b = 0,key_st = 0,key_sel = 0,key_up = 0,key_dn = 0,key_l = 0,key_r = 0;
13 assign buttons = {key_st,key_sel,key_b,key_a,key_dn,key_up,key_l,key_r};
15 /* Clock debouncing */
17 reg [5:0] debounce = 0;
19 reg [9:0] resetcountdown = 0;
21 always @(posedge clk) begin
22 if (inclk != lastinclk) begin
25 resetcountdown <= 10'b1111111111;
26 end else if (debounce == 0) begin
28 resetcountdown <= resetcountdown - 1;
30 debounce <= debounce + 1;
33 always @(negedge fixedclk) begin
34 if (resetcountdown == 0)
36 else if (bitcount == 10) begin
38 if(parity != (^ key)) begin
78 {key_a,key_b,key_st,key_sel,key_up,key_dn,key_l,key_r} <= 8'b0;
81 bitcount <= bitcount + 1;