Finish splitting out functions.
[fpgaboy.git] / insn_incdec16.v
1 `ifdef EXECUTE
2         `INSN_INCDEC16: begin
3                 case (cycle)
4                 0:      begin
5                                 case (opcode[5:4])
6                                 `INSN_reg16_BC: begin
7                                         tmp <= registers[`REG_B];
8                                         tmp2 <= registers[`REG_C];
9                                 end
10                                 `INSN_reg16_DE: begin
11                                         tmp <= registers[`REG_D];
12                                         tmp2 <= registers[`REG_E];
13                                 end
14                                 `INSN_reg16_HL: begin
15                                         tmp <= registers[`REG_H];
16                                         tmp2 <= registers[`REG_L];
17                                 end
18                                 `INSN_reg16_SP: begin
19                                         tmp <= registers[`REG_SPH];
20                                         tmp2 <= registers[`REG_SPL];
21                                 end
22                                 endcase
23                         end
24                 1:      begin
25                                 `EXEC_INC_PC;
26                                 `EXEC_NEWCYCLE;
27                         end
28                 endcase
29         end
30 `endif
31
32 `ifdef WRITEBACK
33         `INSN_INCDEC16: begin
34                 case (cycle)
35                 0:      {tmp,tmp2} <= {tmp,tmp2} +
36                                 (opcode[3] ? 16'hFFFF : 16'h0001);
37                 1: begin
38                                 case (opcode[5:4])
39                                 `INSN_reg16_BC: begin
40                                         registers[`REG_B] <= tmp;
41                                         registers[`REG_C] <= tmp2;
42                                 end
43                                 `INSN_reg16_DE: begin
44                                         registers[`REG_D] <= tmp;
45                                         registers[`REG_E] <= tmp2;
46                                 end
47                                 `INSN_reg16_HL: begin
48                                         registers[`REG_H] <= tmp;
49                                         registers[`REG_L] <= tmp2;
50                                 end
51                                 `INSN_reg16_SP: begin
52                                         registers[`REG_SPH] <= tmp;
53                                         registers[`REG_SPL] <= tmp2;
54                                 end
55                                 endcase
56                         end
57                 endcase
58         end
59 `endif
This page took 0.023578 seconds and 4 git commands to generate.