Finish splitting out functions.
[fpgaboy.git] / GBZ80Core.v
1 `define REG_A   0
2 `define REG_B   1
3 `define REG_C   2
4 `define REG_D   3
5 `define REG_E   4
6 `define REG_F   5
7 `define REG_H   6
8 `define REG_L   7
9 `define REG_SPH 8
10 `define REG_SPL 9
11 `define REG_PCH 10
12 `define REG_PCL 11
13
14 `define FLAG_Z  8'b10000000
15 `define FLAG_N  8'b01000000
16 `define FLAG_H  8'b00100000
17 `define FLAG_C  8'b00010000
18
19 `define STATE_FETCH             2'h0
20 `define STATE_DECODE            2'h1
21 `define STATE_EXECUTE           2'h2
22 `define STATE_WRITEBACK         2'h3
23
24 `define INSN_LD_reg_imm8        8'b00xxx110
25 `define INSN_HALT               8'b01110110
26 `define INSN_LD_HL_reg          8'b01110xxx
27 `define INSN_LD_reg_HL          8'b01xxx110
28 `define INSN_LD_reg_reg         8'b01xxxxxx
29 `define INSN_LD_reg_imm16       8'b00xx0001
30 `define INSN_LD_SP_HL           8'b11111001
31 `define INSN_PUSH_reg           8'b11xx0101
32 `define INSN_POP_reg            8'b11xx0001
33 `define INSN_LDH_AC             8'b111x0010     // Either LDH A,(C) or LDH (C),A
34 `define INSN_LDx_AHL            8'b001xx010     // LDD/LDI A,(HL) / (HL),A
35 `define INSN_ALU8               8'b10xxxxxx     // 10 xxx yyy
36 `define INSN_NOP                8'b00000000
37 `define INSN_RST                8'b11xxx111
38 `define INSN_RET                8'b110x1001     // 1 = RETI, 0 = RET
39 `define INSN_RETCC              8'b110xx000
40 `define INSN_CALL               8'b11001101
41 `define INSN_CALLCC             8'b110xx100     // Not that call/cc.
42 `define INSN_JP_imm             8'b11000011
43 `define INSN_JPCC_imm           8'b110xx010
44 `define INSN_ALU_A              8'b00xxx111
45 `define INSN_JP_HL              8'b11101001
46 `define INSN_JR_imm             8'b00011000
47 `define INSN_JRCC_imm           8'b001xx000
48 `define INSN_INCDEC16           8'b00xxx011
49 `define INSN_VOP_INTR           8'b11111100     // 0xFC is grabbed by the fetch if there is an interrupt pending.
50 `define INSN_DI                 8'b11110011
51 `define INSN_EI                 8'b11111011
52
53 `define INSN_cc_NZ              2'b00
54 `define INSN_cc_Z               2'b01
55 `define INSN_cc_NC              2'b10
56 `define INSN_cc_C               2'b11
57
58 `define INSN_reg_A              3'b111
59 `define INSN_reg_B              3'b000
60 `define INSN_reg_C              3'b001
61 `define INSN_reg_D              3'b010
62 `define INSN_reg_E              3'b011
63 `define INSN_reg_H              3'b100
64 `define INSN_reg_L              3'b101
65 `define INSN_reg_dHL            3'b110
66 `define INSN_reg16_BC           2'b00
67 `define INSN_reg16_DE           2'b01
68 `define INSN_reg16_HL           2'b10
69 `define INSN_reg16_SP           2'b11
70 `define INSN_stack_AF           2'b11
71 `define INSN_stack_BC           2'b00
72 `define INSN_stack_DE           2'b01
73 `define INSN_stack_HL           2'b10
74 `define INSN_alu_ADD            3'b000
75 `define INSN_alu_ADC            3'b001
76 `define INSN_alu_SUB            3'b010
77 `define INSN_alu_SBC            3'b011
78 `define INSN_alu_AND            3'b100
79 `define INSN_alu_XOR            3'b101
80 `define INSN_alu_OR             3'b110
81 `define INSN_alu_CP             3'b111          // Oh lawd, is dat some CP?
82 `define INSN_alu_RLCA           3'b000
83 `define INSN_alu_RRCA           3'b001
84 `define INSN_alu_RLA            3'b010
85 `define INSN_alu_RRA            3'b011
86 `define INSN_alu_DAA            3'b100
87 `define INSN_alu_CPL            3'b101
88 `define INSN_alu_SCF            3'b110
89 `define INSN_alu_CCF            3'b111
90
91 module GBZ80Core(
92         input clk,
93         output reg [15:0] busaddress,   /* BUS_* is latched on STATE_FETCH. */
94         inout [7:0] busdata,
95         output reg buswr, output reg busrd,
96         input irq, input [7:0] jaddr);
97         
98         reg [1:0] state;                                        /* State within this bus cycle (see STATE_*). */
99         reg [2:0] cycle;                                        /* Cycle for instructions. */
100         
101         reg [7:0] registers[11:0];
102         
103         reg [15:0] address;                             /* Address for the next bus operation. */
104         
105         reg [7:0] opcode;                               /* Opcode from the current machine cycle. */
106         
107         reg [7:0] rdata, wdata;         /* Read data from this bus cycle, or write data for the next. */
108         reg rd, wr, newcycle;
109         
110         reg [7:0] tmp, tmp2;                    /* Generic temporary regs. */
111         
112         reg [7:0] buswdata;
113         assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
114         
115         reg ie, iedelay;
116         
117         initial begin
118                 registers[ 0] <= 0;
119                 registers[ 1] <= 0;
120                 registers[ 2] <= 0;
121                 registers[ 3] <= 0;
122                 registers[ 4] <= 0;
123                 registers[ 5] <= 0;
124                 registers[ 6] <= 0;
125                 registers[ 7] <= 0;
126                 registers[ 8] <= 0;
127                 registers[ 9] <= 0;
128                 registers[10] <= 0;
129                 registers[11] <= 0;
130                 rd <= 1;
131                 wr <= 0;
132                 newcycle <= 1;
133                 state <= 0;
134                 cycle <= 0;
135                 busrd <= 0;
136                 buswr <= 0;
137                 busaddress <= 0;
138                 ie <= 0;
139                 iedelay <= 0;
140                 opcode <= 0;
141                 state <= `STATE_WRITEBACK;
142                 cycle <= 0;
143         end
144
145         always @(posedge clk)
146                 case (state)
147                 `STATE_FETCH: begin
148                         if (newcycle) begin
149                                 busaddress <= {registers[`REG_PCH], registers[`REG_PCL]};
150                                 buswr <= 0;
151                                 busrd <= 1;
152                         end else begin
153                                 busaddress <= address;
154                                 buswr <= wr;
155                                 busrd <= rd;
156                                 if (wr)
157                                         buswdata <= wdata;
158                         end
159                         state <= `STATE_DECODE;
160                 end
161                 `STATE_DECODE: begin
162                         if (newcycle) begin
163                                 if (ie && irq)
164                                         opcode <= `INSN_VOP_INTR;
165                                 else
166                                         opcode <= busdata;
167                                 rdata <= busdata;
168                                 newcycle <= 0;
169                                 cycle <= 0;
170                         end else begin
171                                 if (rd) rdata <= busdata;
172                                 cycle <= cycle + 1;
173                         end
174                         if (iedelay) begin
175                                 ie <= 1;
176                                 iedelay <= 0;
177                         end
178                         buswr <= 0;
179                         busrd <= 0;
180                         wr <= 0;
181                         rd <= 0;
182                         address <= 16'bxxxxxxxxxxxxxxxx;        // Make it obvious if something of type has happened.
183                         wdata <= 8'bxxxxxxxx;
184                         state <= `STATE_EXECUTE;
185                 end
186                 `STATE_EXECUTE: begin
187 `define EXEC_INC_PC \
188         {registers[`REG_PCH], registers[`REG_PCL]} <= {registers[`REG_PCH], registers[`REG_PCL]} + 1
189 `define EXEC_NEXTADDR_PCINC \
190         address <= {registers[`REG_PCH], registers[`REG_PCL]} + 1
191 `define EXEC_NEWCYCLE \
192         newcycle <= 1; rd <= 1; wr <= 0
193                         casex (opcode)
194                         `define EXECUTE
195                         `include "allinsns.v"
196                         `undef EXECUTE
197                         `INSN_DI: begin
198                                 `EXEC_NEWCYCLE;
199                                 `EXEC_INC_PC;
200                         end
201                         `INSN_EI: begin
202                                 `EXEC_NEWCYCLE;
203                                 `EXEC_INC_PC;
204                         end
205                         default:
206                                 $stop;
207                         endcase
208                         state <= `STATE_WRITEBACK;
209                 end
210                 `STATE_WRITEBACK: begin
211                         casex (opcode)
212                         `define WRITEBACK
213                         `include "allinsns.v"
214                         `undef WRITEBACK
215                         default:
216                                 $stop;
217                         endcase
218                         state <= `STATE_FETCH;
219                 end
220                 endcase
221 endmodule
This page took 0.029106 seconds and 4 git commands to generate.