dc70cc0d9d7a49cab58aec6a2ba9a8ae05e4070e
[fpgaboy.git] / System.v
1
2 `timescale 1ns / 1ps
3 module ROM(
4         input [15:0] address,
5         inout [7:0] data,
6         input clk,
7         input wr, rd);
8
9         reg [7:0] rom [1023:0];
10         initial $readmemh("rom.hex", rom);
11
12         wire decode = address[15:13] == 0;
13         wire [7:0] odata = rom[address[10:0]];
14         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
15         //assign data = rd ? odata : 8'bzzzzzzzz;
16 endmodule
17
18 module MiniRAM(                 /* XXX will need to go INSIDE the CPU for when we do DMA */
19         input [15:0] address,
20         inout [7:0] data,
21         input clk,
22         input wr, rd);
23         
24         reg [7:0] ram [127:0];
25         
26         wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
27         reg [7:0] odata;
28         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
29         
30         always @(negedge clk)
31         begin
32                 if (decode)     // This has to go this way. The only way XST knows how to do
33                 begin                           // block ram is chip select, write enable, and always
34                         if (wr)         // reading. "else if rd" does not cut it ...
35                                 ram[address[6:0]] <= data;
36                         odata <= ram[address[6:0]];
37                 end
38         end
39 endmodule
40
41 module InternalRAM(
42         input [15:0] address,
43         inout [7:0] data,
44         input clk,
45         input wr, rd);
46         
47         // synthesis attribute ram_style of ram is block
48         reg [7:0] ram [8191:0];
49         
50         wire decode = address[15:13] == 3'b110;
51         reg [7:0] odata;
52         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
53         
54         always @(negedge clk)
55         begin
56                 if (decode)     // This has to go this way. The only way XST knows how to do
57                 begin                           // block ram is chip select, write enable, and always
58                         if (wr)         // reading. "else if rd" does not cut it ...
59                                 ram[address[12:0]] <= data;
60                         odata <= ram[address[12:0]];
61                 end
62         end
63 endmodule
64
65 module Switches(
66         input [15:0] address,
67         inout [7:0] data,
68         input clk,
69         input wr, rd,
70         input [7:0] switches,
71         output reg [7:0] ledout = 0);
72         
73         wire decode = address == 16'hFF51;
74         reg [7:0] odata;
75         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
76         
77         always @(negedge clk)
78         begin
79                 if (decode && rd)
80                         odata <= switches;
81                 else if (decode && wr)
82                         ledout <= data;
83         end
84 endmodule
85
86 module CoreTop(
87         input xtal,
88         input [7:0] switches,
89         input [3:0] buttons,
90         output wire [7:0] leds,
91         output serio,
92         output wire [3:0] digits,
93         output wire [7:0] seven,
94         output wire hs, vs,
95         output wire [2:0] r, g,
96         output wire [1:0] b,
97         output wire soundl, soundr);
98         
99         wire xtalb, clk, vgaclk;
100         IBUFG iclkbuf(.O(xtalb), .I(xtal));
101         CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
102         pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
103         
104         wire [15:0] addr;       
105         wire [7:0] data;
106         wire wr, rd;
107         
108         wire irq, tmrirq, lcdcirq, vblankirq;
109         wire [7:0] jaddr;
110         wire [1:0] state;
111         
112         GBZ80Core core(
113                 .clk(clk),
114                 .busaddress(addr),
115                 .busdata(data),
116                 .buswr(wr),
117                 .busrd(rd),
118                 .irq(irq),
119                 .jaddr(jaddr),
120                 .state(state));
121         
122         ROM rom(
123                 .address(addr),
124                 .data(data),
125                 .clk(clk),
126                 .wr(wr),
127                 .rd(rd));
128         
129         wire lcdhs, lcdvs, lcdclk;
130         wire [2:0] lcdr, lcdg;
131         wire [1:0] lcdb;
132         
133         LCDC lcdc(
134                 .addr(addr),
135                 .data(data),
136                 .clk(clk),
137                 .wr(wr),
138                 .rd(rd),
139                 .lcdcirq(lcdcirq),
140                 .vblankirq(vblankirq),
141                 .lcdclk(lcdclk),
142                 .lcdhs(lcdhs),
143                 .lcdvs(lcdvs),
144                 .lcdr(lcdr),
145                 .lcdg(lcdg),
146                 .lcdb(lcdb));
147         
148         Framebuffer fb(
149                 .lcdclk(lcdclk),
150                 .lcdhs(lcdhs),
151                 .lcdvs(lcdvs),
152                 .lcdr(lcdr),
153                 .lcdg(lcdg),
154                 .lcdb(lcdb),
155                 .vgaclk(vgaclk),
156                 .vgahs(hs),
157                 .vgavs(vs),
158                 .vgar(r),
159                 .vgag(g),
160                 .vgab(b));
161         
162         AddrMon amon(
163                 .addr(addr), 
164                 .clk(clk), 
165                 .digit(digits), 
166                 .out(seven),
167                 .freeze(buttons[0]),
168                 .periods(
169                         (state == 2'b00) ? 4'b0010 :
170                         (state == 2'b01) ? 4'b0001 :
171                         (state == 2'b10) ? 4'b1000 :
172                                            4'b0100) );
173          
174         Switches sw(
175                 .address(addr),
176                 .data(data),
177                 .clk(clk),
178                 .wr(wr),
179                 .rd(rd),
180                 .ledout(leds),
181                 .switches(switches)
182                 );
183
184         UART nouart (   /* no u */
185                 .clk(clk), 
186                 .wr(wr), 
187                 .rd(rd), 
188                 .addr(addr), 
189                 .data(data), 
190                 .serial(serio)
191                 );
192
193         InternalRAM ram(
194                 .address(addr),
195                 .data(data),
196                 .clk(clk),
197                 .wr(wr),
198                 .rd(rd)
199                 );
200         
201         MiniRAM mram(
202                 .address(addr),
203                 .data(data),
204                 .clk(clk),
205                 .wr(wr),
206                 .rd(rd)
207                 );
208
209         Timer tmr(
210                 .clk(clk),
211                 .wr(wr),
212                 .rd(rd),
213                 .addr(addr),
214                 .data(data),
215                 .irq(tmrirq)
216                 );
217         
218         Interrupt intr(
219                 .clk(clk),
220                 .rd(rd),
221                 .wr(wr),
222                 .addr(addr),
223                 .data(data),
224                 .vblank(vblankirq),
225                 .lcdc(lcdcirq),
226                 .tovf(tmrirq),
227                 .serial(0),
228                 .buttons(0),
229                 .master(irq),
230                 .jaddr(jaddr));
231         
232         Soundcore sound(
233                 .core_clk(clk),
234                 .rd(rd),
235                 .wr(wr),
236                 .addr(addr),
237                 .data(data),
238                 .snd_data_l(soundl),
239                 .snd_data_r(soundr));
240 endmodule
241
242 module TestBench();
243         reg clk = 1;
244         wire [15:0] addr;
245         wire [7:0] data;
246         wire wr, rd;
247         
248         wire irq, tmrirq;
249         wire [7:0] jaddr;
250         
251         wire [7:0] leds;
252         wire [7:0] switches;
253         
254         always #62 clk <= ~clk;
255         GBZ80Core core(
256                 .clk(clk),
257                 .busaddress(addr),
258                 .busdata(data),
259                 .buswr(wr),
260                 .busrd(rd),
261                 .irq(irq),
262                 .jaddr(jaddr));
263         
264         ROM rom(
265                 .clk(clk),
266                 .address(addr),
267                 .data(data),
268                 .wr(wr),
269                 .rd(rd));
270         
271         InternalRAM ram(
272                 .address(addr),
273                 .data(data),
274                 .clk(clk),
275                 .wr(wr),
276                 .rd(rd));
277
278         wire serio;
279         UART uart(
280                 .addr(addr),
281                 .data(data),
282                 .clk(clk),
283                 .wr(wr),
284                 .rd(rd),
285                 .serial(serio));
286         
287         Timer tmr(
288                 .clk(clk),
289                 .wr(wr),
290                 .rd(rd),
291                 .addr(addr),
292                 .data(data),
293                 .irq(tmrirq));
294         
295         Interrupt intr(
296                 .clk(clk),
297                 .rd(rd),
298                 .wr(wr),
299                 .addr(addr),
300                 .data(data),
301                 .vblank(0),
302                 .lcdc(0),
303                 .tovf(tmrirq),
304                 .serial(0),
305                 .buttons(0),
306                 .master(irq),
307                 .jaddr(jaddr));
308         
309         Switches sw(
310                 .clk(clk),
311                 .address(addr),
312                 .data(data),
313                 .wr(wr),
314                 .rd(rd),
315                 .switches(switches),
316                 .ledout(leds));
317 endmodule
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