Merge branch 'master' of lu@anyus.res.cmu.edu:/storage/fpga/FPGABoy
[fpgaboy.git] / PS2Button.v
1 module PS2Button(
2         input inclk,
3         input indata,
4         input rst,
5         output outclk,
6         output outdata,
7         output reg [7:0] buttons
8         );
9
10         assign outdata = 1'b1;
11         assign outclk = 1'b1;
12
13         reg bitcount [3:0] = 0;
14         reg [7:0] key;
15         reg keyarrow, keyup, parity;
16         reg key_a,key_b,key_st,key_sel,key_up,key_dn,key_l,key_r;
17
18         assign buttons = {key_st,key_sel,key_b,key_a,key_dn,key_up,key_l,key_r};
19
20         always @ (negedge inclk) begin
21                 if(bitcount == 10) begin
22                         bitcount <= 0;
23                         if(parity == (^ key)) begin
24                                 if(keyarrow) begin
25                                         keyarrow <= 0;
26                                         case(key)
27                                                 8'hF0: keyup <= 1;
28                                                 8'h75: key_up <= 1;
29                                                 8'h74: key_r <= 1;
30                                                 8'h72: key_dn <= 1;
31                                                 8'h6B: key_l <= 1;
32                                         endcase
33                                 end
34                                 else begin
35                                         if(keyup) begin
36                                                 keyup <= 0;
37                                                 case(key)
38                                                         8'h75: key_up <= 0;
39                                                         8'h74: key_r <= 0;
40                                                         8'h72: key_dn <= 0;
41                                                         8'h6B: key_l <= 0;
42                                                         8'h1C: key_a <= 0;
43                                                         8'h1B: key_b <= 0;
44                                                         8'h5A: key_st <= 0;
45                                                         8'h59: key_sel <= 0;
46                                                 endcase
47                                         end
48                                         else begin
49                                                 case(key)
50                                                         8'hE0: keyarrow <= 1;
51                                                         8'hF0: keyup <= 1;
52                                                         8'h1C: key_a <= 1;
53                                                         8'h1B: key_b <= 1;
54                                                         8'h5A: key_st <= 1;
55                                                         8'h59: key_sel <= 1;
56                                                 endcase
57                                         end
58                                 end
59                         end
60                         else begin
61                                 keyarrow <= 0;
62                                 keyup <= 0;
63                                 {key_a,key_b,key_st,key_sel,key_up,key_dn,key_l,key_r} <= 8'b0;
64                         end
65                 end else
66                         bitcount <= bitcount + 1;
67
68                 case(bitcount)
69                         1: key[0] <= indata;
70                         2: key[1] <= indata;
71                         3: key[2] <= indata;
72                         4: key[3] <= indata;
73                         5: key[4] <= indata;
74                         6: key[5] <= indata;
75                         7: key[6] <= indata;
76                         8: key[7] <= indata;
77                         9: parity <= indata;
78                 endcase
79         end
80
81 endmodule
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