System.v

   1
   2 `timescale 1ns / 1ps
   3 module ROM(
   4         input [15:0] address,
   5         inout [7:0] data,
   6         input clk,
   7         input wr, rd);
   8
   9         reg [7:0] rom [1023:0];
  10         initial $readmemh("rom.hex", rom);
  11
  12         wire decode = address[15:13] == 0;
  13         wire [7:0] odata = rom[address[10:0]];
  14         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
  15         //assign data = rd ? odata : 8'bzzzzzzzz;
  16 endmodule
  17
  18 module MiniRAM(                 /* XXX will need to go INSIDE the CPU for when we do DMA */
  19         input [15:0] address,
  20         inout [7:0] data,
  21         input clk,
  22         input wr, rd);
  23
  24         reg [7:0] ram [127:0];
  25
  26         wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
  27         reg [7:0] odata;
  28         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
  29
  30         always @(negedge clk)
  31         begin
  32                 if (decode)     // This has to go this way. The only way XST knows how to do
  33                 begin                           // block ram is chip select, write enable, and always
  34                         if (wr)         // reading. "else if rd" does not cut it ...
  35                                 ram[address[6:0]] <= data;
  36                         odata <= ram[address[6:0]];
  37                 end
  38         end
  39 endmodule
  40
  41 module InternalRAM(
  42         input [15:0] address,
  43         inout [7:0] data,
  44         input clk,
  45         input wr, rd);
  46
  47         // synthesis attribute ram_style of ram is block
  48         reg [7:0] ram [8191:0];
  49
  50         wire decode = address[15:13] == 3'b110;
  51         reg [7:0] odata;
  52         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
  53
  54         always @(negedge clk)
  55         begin
  56                 if (decode)     // This has to go this way. The only way XST knows how to do
  57                 begin                           // block ram is chip select, write enable, and always
  58                         if (wr)         // reading. "else if rd" does not cut it ...
  59                                 ram[address[12:0]] <= data;
  60                         odata <= ram[address[12:0]];
  61                 end
  62         end
  63 endmodule
  64
  65 module Switches(
  66         input [15:0] address,
  67         inout [7:0] data,
  68         input clk,
  69         input wr, rd,
  70         input [7:0] switches,
  71         output reg [7:0] ledout = 0);
  72
  73         wire decode = address == 16'hFF51;
  74         reg [7:0] odata;
  75         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
  76
  77         always @(negedge clk)
  78         begin
  79                 if (decode && rd)
  80                         odata <= switches;
  81                 else if (decode && wr)
  82                         ledout <= data;
  83         end
  84 endmodule
  85
  86 module CoreTop(
  87         input xtal,
  88         input [7:0] switches,
  89         input [3:0] buttons,
  90         output wire [7:0] leds,
  91         output serio,
  92         output wire [3:0] digits,
  93         output wire [7:0] seven,
  94         output wire hs, vs,
  95         output wire [2:0] r, g,
  96         output wire [1:0] b);
  97
  98         wire xtalb, clk, vgaclk;
  99         IBUFG iclkbuf(.O(xtalb), .I(xtal));
 100         CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
 101         pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
 102
 103         wire [15:0] addr;
 104         wire [7:0] data;
 105         wire wr, rd;
 106
 107         wire irq, tmrirq, lcdcirq, vblankirq;
 108         wire [7:0] jaddr;
 109         wire [1:0] state;
 110
 111         GBZ80Core core(
 112                 .clk(clk),
 113                 .busaddress(addr),
 114                 .busdata(data),
 115                 .buswr(wr),
 116                 .busrd(rd),
 117                 .irq(irq),
 118                 .jaddr(jaddr),
 119                 .state(state));
 120
 121         ROM rom(
 122                 .address(addr),
 123                 .data(data),
 124                 .clk(clk),
 125                 .wr(wr),
 126                 .rd(rd));
 127
 128         wire lcdhs, lcdvs, lcdclk;
 129         wire [2:0] lcdr, lcdg;
 130         wire [1:0] lcdb;
 131
 132         LCDC lcdc(
 133                 .addr(addr),
 134                 .data(data),
 135                 .clk(clk),
 136                 .wr(wr),
 137                 .rd(rd),
 138                 .lcdcirq(lcdcirq),
 139                 .vblankirq(vblankirq),
 140                 .lcdclk(lcdclk),
 141                 .lcdhs(lcdhs),
 142                 .lcdvs(lcdvs),
 143                 .lcdr(lcdr),
 144                 .lcdg(lcdg),
 145                 .lcdb(lcdb));
 146
 147         Framebuffer fb(
 148                 .lcdclk(lcdclk),
 149                 .lcdhs(lcdhs),
 150                 .lcdvs(lcdvs),
 151                 .lcdr(lcdr),
 152                 .lcdg(lcdg),
 153                 .lcdb(lcdb),
 154                 .vgaclk(vgaclk),
 155                 .vgahs(hs),
 156                 .vgavs(vs),
 157                 .vgar(r),
 158                 .vgag(g),
 159                 .vgab(b));
 160
 161         AddrMon amon(
 162                 .addr(addr),
 163                 .clk(clk),
 164                 .digit(digits),
 165                 .out(seven),
 166                 .freeze(buttons[0]),
 167                 .periods(
 168                         (state == 2'b00) ? 4'b0010 :
 169                         (state == 2'b01) ? 4'b0001 :
 170                         (state == 2'b10) ? 4'b1000 :
 171                                            4'b0100) );
 172
 173         Switches sw(
 174                 .address(addr),
 175                 .data(data),
 176                 .clk(clk),
 177                 .wr(wr),
 178                 .rd(rd),
 179                 .ledout(leds),
 180                 .switches(switches)
 181                 );
 182
 183         UART nouart (   /* no u */
 184                 .clk(clk),
 185                 .wr(wr),
 186                 .rd(rd),
 187                 .addr(addr),
 188                 .data(data),
 189                 .serial(serio)
 190                 );
 191
 192         InternalRAM ram(
 193                 .address(addr),
 194                 .data(data),
 195                 .clk(clk),
 196                 .wr(wr),
 197                 .rd(rd)
 198                 );
 199
 200         MiniRAM mram(
 201                 .address(addr),
 202                 .data(data),
 203                 .clk(clk),
 204                 .wr(wr),
 205                 .rd(rd)
 206                 );
 207
 208         Timer tmr(
 209                 .clk(clk),
 210                 .wr(wr),
 211                 .rd(rd),
 212                 .addr(addr),
 213                 .data(data),
 214                 .irq(tmrirq)
 215                 );
 216
 217         Interrupt intr(
 218                 .clk(clk),
 219                 .rd(rd),
 220                 .wr(wr),
 221                 .addr(addr),
 222                 .data(data),
 223                 .vblank(vblankirq),
 224                 .lcdc(lcdcirq),
 225                 .tovf(tmrirq),
 226                 .serial(0),
 227                 .buttons(0),
 228                 .master(irq),
 229                 .jaddr(jaddr));
 230 endmodule
 231
 232 module TestBench();
 233         reg clk = 1;
 234         wire [15:0] addr;
 235         wire [7:0] data;
 236         wire wr, rd;
 237
 238         wire irq, tmrirq;
 239         wire [7:0] jaddr;
 240
 241         wire [7:0] leds;
 242         wire [7:0] switches;
 243
 244         always #62 clk <= ~clk;
 245         GBZ80Core core(
 246                 .clk(clk),
 247                 .busaddress(addr),
 248                 .busdata(data),
 249                 .buswr(wr),
 250                 .busrd(rd),
 251                 .irq(irq),
 252                 .jaddr(jaddr));
 253
 254         ROM rom(
 255                 .clk(clk),
 256                 .address(addr),
 257                 .data(data),
 258                 .wr(wr),
 259                 .rd(rd));
 260
 261         InternalRAM ram(
 262                 .address(addr),
 263                 .data(data),
 264                 .clk(clk),
 265                 .wr(wr),
 266                 .rd(rd));
 267
 268         wire serio;
 269         UART uart(
 270                 .addr(addr),
 271                 .data(data),
 272                 .clk(clk),
 273                 .wr(wr),
 274                 .rd(rd),
 275                 .serial(serio));
 276
 277         Timer tmr(
 278                 .clk(clk),
 279                 .wr(wr),
 280                 .rd(rd),
 281                 .addr(addr),
 282                 .data(data),
 283                 .irq(tmrirq));
 284
 285         Interrupt intr(
 286                 .clk(clk),
 287                 .rd(rd),
 288                 .wr(wr),
 289                 .addr(addr),
 290                 .data(data),
 291                 .vblank(0),
 292                 .lcdc(0),
 293                 .tovf(tmrirq),
 294                 .serial(0),
 295                 .buttons(0),
 296                 .master(irq),
 297                 .jaddr(jaddr));
 298
 299         Switches sw(
 300                 .clk(clk),
 301                 .address(addr),
 302                 .data(data),
 303                 .wr(wr),
 304                 .rd(rd),
 305                 .switches(switches),
 306                 .ledout(leds));
 307 endmodule