7seg.v

   1 module AddrMon(
   2         input [15:0] addr,
   3         input clk,
   4         output reg [3:0] digit,
   5         output reg [7:0] out,
   6         input freeze
   7         );
   8
   9         reg [5:0] clkdv;
  10         reg [1:0] dcount;
  11
  12         reg [15:0] latch = 0;
  13
  14         wire [3:0] curval =
  15                 (dcount == 2'b00) ? latch[3:0]  :
  16                 (dcount == 2'b01) ? latch[7:4]  :
  17                 (dcount == 2'b10) ? latch[11:8] :
  18                                      latch[15:12];
  19
  20         always @ (negedge clk) begin
  21                 if (clkdv == 31) begin
  22                         clkdv <= 0;
  23                         dcount <= dcount + 1;
  24
  25                         case(dcount)
  26                         2'b00: digit <= 4'b1110;
  27                         2'b01: digit <= 4'b1101;
  28                         2'b10: digit <= 4'b1011;
  29                         2'b11: digit <= 4'b0111;
  30                         endcase
  31
  32                         case(curval)
  33                                                         /* ABCDEFGP */
  34                         4'h0: out <= ~8'b11111100;
  35                         4'h1: out <= ~8'b01100000;
  36                         4'h2: out <= ~8'b11011010;
  37                         4'h3: out <= ~8'b11110010;
  38                         4'h4: out <= ~8'b01100110;
  39                         4'h5: out <= ~8'b10110110;
  40                         4'h6: out <= ~8'b10111110;
  41                         4'h7: out <= ~8'b11100000;
  42                         4'h8: out <= ~8'b11111110;
  43                         4'h9: out <= ~8'b11110110;
  44                         4'hA: out <= ~8'b11101110;
  45                         4'hB: out <= ~8'b00111110;
  46                         4'hC: out <= ~8'b10011100;
  47                         4'hD: out <= ~8'b01111010;
  48                         4'hE: out <= ~8'b10011110;
  49                         4'hF: out <= ~8'b10001110;
  50                         endcase
  51                 end else
  52                         clkdv <= clkdv + 1;
  53                 if (~freeze)
  54                         latch <= addr;
  55         end
  56 endmodule