System.v

   1
   2 `timescale 1ns / 1ps
   3 module SimROM(
   4         input [15:0] address,
   5         inout [7:0] data,
   6         input clk,
   7         input wr, rd);
   8
   9         reg rdlatch = 0;
  10         reg [7:0] odata;
  11
  12         reg [7:0] rom [32767:0];
  13         initial $readmemh("rom.hex", rom);
  14
  15         wire decode = address[15:13] == 0;
  16         always @(posedge clk) begin
  17                 rdlatch <= rd && decode;
  18                 odata <= rom[address[10:0]];
  19         end
  20         assign data = rdlatch ? odata : 8'bzzzzzzzz;
  21 endmodule
  22
  23 module BootstrapROM(
  24         input [15:0] address,
  25         inout [7:0] data,
  26         input clk,
  27         input wr, rd);
  28
  29         reg rdlatch = 0;
  30         reg [7:0] addrlatch = 0;
  31         reg romno = 0, romnotmp = 0;
  32         reg [7:0] brom0 [255:0];
  33         reg [7:0] brom1 [255:0];
  34
  35         initial $readmemh("fpgaboot.hex", brom0);
  36         initial $readmemh("gbboot.hex", brom1);
  37
  38 `ifdef isim
  39         initial romno <= 1;
  40 `endif
  41
  42         wire decode = address[15:8] == 0;
  43         wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];
  44         always @(posedge clk) begin
  45                 rdlatch <= rd && decode;
  46                 addrlatch <= address[7:0];
  47                 if (wr && decode) romnotmp <= data[0];
  48                 if (rd && address == 16'h0000) romno <= romnotmp;       /* Latch when the program restarts. */
  49         end
  50         assign data = rdlatch ? odata : 8'bzzzzzzzz;
  51 endmodule
  52
  53 module MiniRAM(
  54         input [15:0] address,
  55         inout [7:0] data,
  56         input clk,
  57         input wr, rd);
  58
  59         reg [7:0] ram [127:0];
  60
  61         wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
  62         reg rdlatch = 0;
  63         reg [7:0] odata;
  64         assign data = rdlatch ? odata : 8'bzzzzzzzz;
  65
  66         always @(posedge clk)
  67         begin
  68                 rdlatch <= rd && decode;
  69                 if (decode)             // This has to go this way. The only way XST knows how to do
  70                 begin                   // block ram is chip select, write enable, and always
  71                         if (wr)         // reading. "else if rd" does not cut it ...
  72                                 ram[address[6:0]] <= data;
  73                         odata <= ram[address[6:0]];
  74                 end
  75         end
  76 endmodule
  77
  78 module CellularRAM(
  79         input clk,
  80         input [15:0] address,
  81         inout [7:0] data,
  82         input wr, rd,
  83         output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
  84         output wire [22:0] cr_A,
  85         inout [15:0] cr_DQ);
  86
  87         parameter ADDR_PROGADDRH = 16'hFF60;
  88         parameter ADDR_PROGADDRM = 16'hFF61;
  89         parameter ADDR_PROGADDRL = 16'hFF62;
  90         parameter ADDR_PROGDATA = 16'hFF63;
  91         parameter ADDR_MBC = 16'hFF64;
  92
  93         reg rdlatch = 0, wrlatch = 0;
  94         reg [15:0] addrlatch = 0;
  95         reg [7:0] datalatch = 0;
  96
  97         reg [7:0] progaddrh, progaddrm, progaddrl;
  98
  99         reg [22:0] progaddr;
 100
 101         reg [7:0] mbc_emul = 8'b00000101;       // High bit is whether we're poking flash
 102                                                 // low 7 bits are the MBC that we are emulating
 103
 104         assign cr_nADV = 0;     /* Addresses are always valid! :D */
 105         assign cr_nCE = 0;      /* The chip is enabled */
 106         assign cr_nLB = 0;      /* Lower byte is enabled */
 107         assign cr_nUB = 0;      /* Upper byte is enabled */
 108         assign cr_CRE = 0;      /* Data writes, not config */
 109         assign cr_CLK = 0;      /* Clock? I think not! */
 110
 111         wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA);
 112
 113         reg [3:0] rambank = 0;
 114         reg [8:0] rombank = 1;
 115
 116         assign cr_nOE = decode ? ~rdlatch : 1;
 117         assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) || (mbc_emul[6:0] == 0))) ? ~wrlatch : 1;
 118
 119         assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
 120         assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom, home bank */ {9'b0,addrlatch[13:0]} :
 121                         (addrlatch[15:14] == 2'b01) ? /* extrom, paged bank */ {rombank, addrlatch[13:0]} :
 122                         (addrlatch[15:13] == 3'b101) ? /* extram */ {1'b1, 5'b0, rambank, addrlatch[12:0]} :
 123                         (addrlatch == ADDR_PROGDATA) ? progaddr :
 124                         23'b0;
 125
 126         always @(posedge clk) begin
 127                 case (address)
 128                 ADDR_PROGADDRH: if (wr) progaddrh <= data;
 129                 ADDR_PROGADDRM: if (wr) progaddrm <= data;
 130                 ADDR_PROGADDRL: if (wr) progaddrl <= data;
 131                 ADDR_PROGDATA:  if (rd || wr) begin
 132                                         progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};
 133                                         {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;
 134                                 end
 135                 ADDR_MBC:       begin
 136                                         mbc_emul <= data;
 137                                         rambank <= 0;
 138                                         rombank <= 1;
 139                                 end
 140                 endcase
 141
 142                 if (mbc_emul[6:0] == 5) begin
 143                         if ((address[15:12] == 4'h2) && wr)
 144                                 rombank <= {rombank[8], data};
 145                         else if ((address[15:12] == 4'h3) && wr)
 146                                 rombank <= {data[0], rombank[7:0]};
 147                         else if ((address[15:12] == 4'h4) && wr)
 148                                 rambank <= data[3:0];
 149                 end
 150
 151                 rdlatch <= rd;
 152                 wrlatch <= wr;
 153                 addrlatch <= address;
 154                 datalatch <= data;
 155         end
 156
 157         assign data = (rdlatch && decode) ?
 158                                 (addrlatch == ADDR_PROGADDRH) ? progaddrh :
 159                                 (addrlatch == ADDR_PROGADDRM) ? progaddrm :
 160                                 (addrlatch == ADDR_PROGADDRL) ? progaddrl :
 161                                 cr_DQ
 162                         : 8'bzzzzzzzz;
 163 endmodule
 164
 165 module InternalRAM(
 166         input [15:0] address,
 167         inout [7:0] data,
 168         input clk,
 169         input wr, rd);
 170
 171         // synthesis attribute ram_style of ram is block
 172         reg [7:0] ram [8191:0];
 173
 174         wire decode = (address >= 16'hC000) && (address <= 16'hFDFF);   /* This includes echo RAM. */
 175         reg [7:0] odata;
 176         reg rdlatch = 0;
 177         assign data = rdlatch ? odata : 8'bzzzzzzzz;
 178
 179         always @(posedge clk)
 180         begin
 181                 rdlatch <= rd && decode;
 182                 if (decode)             // This has to go this way. The only way XST knows how to do
 183                 begin                   // block ram is chip select, write enable, and always
 184                         if (wr)         // reading. "else if rd" does not cut it ...
 185                                 ram[address[12:0]] <= data;
 186                         odata <= ram[address[12:0]];
 187                 end
 188         end
 189 endmodule
 190
 191 module Switches(
 192         input [15:0] address,
 193         inout [7:0] data,
 194         input clk,
 195         input wr, rd,
 196         input [7:0] switches,
 197         output reg [7:0] ledout = 0);
 198
 199         wire decode = address == 16'hFF51;
 200         reg [7:0] odata;
 201         reg rdlatch = 0;
 202         assign data = rdlatch ? odata : 8'bzzzzzzzz;
 203
 204         always @(posedge clk)
 205         begin
 206                 rdlatch <= rd && decode;
 207                 if (decode && rd)
 208                         odata <= switches;
 209                 else if (decode && wr)
 210                         ledout <= data;
 211         end
 212 endmodule
 213
 214 `ifdef isim
 215 module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
 216 endmodule
 217 `endif
 218
 219 module CoreTop(
 220 `ifdef isim
 221         output reg vgaclk = 0,
 222         output reg clk = 0,
 223 `else
 224         input xtal,
 225         input [7:0] switches,
 226         input [3:0] buttons,
 227         output wire [7:0] leds,
 228         output serio,
 229         input serin,
 230         output wire [3:0] digits,
 231         output wire [7:0] seven,
 232         output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
 233         output wire [22:0] cr_A,
 234         inout [15:0] cr_DQ,
 235 `endif
 236         output wire hs, vs,
 237         output wire [2:0] r, g,
 238         output wire [1:0] b,
 239         output wire soundl, soundr);
 240
 241 `ifdef isim
 242         always #62 clk <= ~clk;
 243         always #100 vgaclk <= ~vgaclk;
 244
 245         Dumpable dump(r,g,b,hs,vs,vgaclk);
 246
 247         wire [7:0] leds;
 248         wire serio;
 249         wire serin = 1;
 250         wire [3:0] digits;
 251         wire [7:0] seven;
 252         wire [7:0] switches = 8'b0;
 253         wire [3:0] buttons = 4'b0;
 254 `else
 255         wire xtalb, clk, vgaclk;
 256         IBUFG iclkbuf(.O(xtalb), .I(xtal));
 257         CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
 258         pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
 259 `endif
 260
 261         wire [15:0] addr [1:0];
 262         wire [7:0] data [1:0];
 263         wire wr [1:0], rd [1:0];
 264
 265         wire irq, tmrirq, lcdcirq, vblankirq;
 266         wire [7:0] jaddr;
 267         wire [1:0] state;
 268
 269         GBZ80Core core(
 270                 .clk(clk),
 271                 .bus0address(addr[0]),
 272                 .bus0data(data[0]),
 273                 .bus0wr(wr[0]),
 274                 .bus0rd(rd[0]),
 275                 .bus1address(addr[1]),
 276                 .bus1data(data[1]),
 277                 .bus1wr(wr[1]),
 278                 .bus1rd(rd[1]),
 279                 .irq(irq),
 280                 .jaddr(jaddr),
 281                 .state(state));
 282
 283         BootstrapROM brom(
 284                 .address(addr[1]),
 285                 .data(data[1]),
 286                 .clk(clk),
 287                 .wr(wr[1]),
 288                 .rd(rd[1]));
 289
 290 `ifdef isim
 291         SimROM rom(
 292                 .address(addr[0]),
 293                 .data(data[0]),
 294                 .clk(clk),
 295                 .wr(wr[0]),
 296                 .rd(rd[0]));
 297 `else
 298         CellularRAM cellram(
 299                 .address(addr[0]),
 300                 .data(data[0]),
 301                 .clk(clk),
 302                 .wr(wr[0]),
 303                 .rd(rd[0]),
 304                 .cr_nADV(cr_nADV),
 305                 .cr_nCE(cr_nCE),
 306                 .cr_nOE(cr_nOE),
 307                 .cr_nWE(cr_nWE),
 308                 .cr_CRE(cr_CRE),
 309                 .cr_nLB(cr_nLB),
 310                 .cr_nUB(cr_nUB),
 311                 .cr_CLK(cr_CLK),
 312                 .cr_A(cr_A),
 313                 .cr_DQ(cr_DQ));
 314 `endif
 315
 316         wire lcdhs, lcdvs, lcdclk;
 317         wire [2:0] lcdr, lcdg;
 318         wire [1:0] lcdb;
 319
 320         LCDC lcdc(
 321                 .clk(clk),
 322                 .addr(addr[0]),
 323                 .data(data[0]),
 324                 .wr(wr[0]),
 325                 .rd(rd[0]),
 326                 .lcdcirq(lcdcirq),
 327                 .vblankirq(vblankirq),
 328                 .lcdclk(lcdclk),
 329                 .lcdhs(lcdhs),
 330                 .lcdvs(lcdvs),
 331                 .lcdr(lcdr),
 332                 .lcdg(lcdg),
 333                 .lcdb(lcdb));
 334
 335         Framebuffer fb(
 336                 .lcdclk(lcdclk),
 337                 .lcdhs(lcdhs),
 338                 .lcdvs(lcdvs),
 339                 .lcdr(lcdr),
 340                 .lcdg(lcdg),
 341                 .lcdb(lcdb),
 342                 .vgaclk(vgaclk),
 343                 .vgahs(hs),
 344                 .vgavs(vs),
 345                 .vgar(r),
 346                 .vgag(g),
 347                 .vgab(b));
 348
 349         Switches sw(
 350                 .clk(clk),
 351                 .address(addr[0]),
 352                 .data(data[0]),
 353                 .wr(wr[0]),
 354                 .rd(rd[0]),
 355                 .ledout(leds),
 356                 .switches(switches)
 357                 );
 358
 359         AddrMon amon(
 360                 .clk(clk),
 361                 .addr(addr[0]),
 362                 .digit(digits),
 363                 .out(seven),
 364                 .freeze(buttons[0]),
 365                 .periods(
 366                         (state == 2'b00) ? 4'b0010 :
 367                         (state == 2'b01) ? 4'b0001 :
 368                         (state == 2'b10) ? 4'b1000 :
 369                                            4'b0100) );
 370
 371         UART nouart (   /* no u */
 372                 .clk(clk),
 373                 .addr(addr[0]),
 374                 .data(data[0]),
 375                 .wr(wr[0]),
 376                 .rd(rd[0]),
 377                 .serial(serio),
 378                 .serialrx(serin)
 379                 );
 380
 381         InternalRAM ram(
 382                 .clk(clk),
 383                 .address(addr[0]),
 384                 .data(data[0]),
 385                 .wr(wr[0]),
 386                 .rd(rd[0])
 387                 );
 388
 389         MiniRAM mram(
 390                 .clk(clk),
 391                 .address(addr[1]),
 392                 .data(data[1]),
 393                 .wr(wr[1]),
 394                 .rd(rd[1])
 395                 );
 396
 397         Timer tmr(
 398                 .clk(clk),
 399                 .addr(addr[0]),
 400                 .data(data[0]),
 401                 .wr(wr[0]),
 402                 .rd(rd[0]),
 403                 .irq(tmrirq)
 404                 );
 405
 406         Interrupt intr(
 407                 .clk(clk),
 408                 .addr(addr[0]),
 409                 .data(data[0]),
 410                 .wr(wr[0]),
 411                 .rd(rd[0]),
 412                 .vblank(vblankirq),
 413                 .lcdc(lcdcirq),
 414                 .tovf(tmrirq),
 415                 .serial(1'b0),
 416                 .buttons(1'b0),
 417                 .master(irq),
 418                 .jaddr(jaddr));
 419
 420         Soundcore sound(
 421                 .core_clk(clk),
 422                 .addr(addr[0]),
 423                 .data(data[0]),
 424                 .rd(rd[0]),
 425                 .wr(wr[0]),
 426                 .snd_data_l(soundl),
 427                 .snd_data_r(soundr));
 428 endmodule