insn_ld_sp_hl.v

   1 `ifdef EXECUTE
   2         `INSN_LD_SP_HL: begin
   3                 case (cycle)
   4                 0:      begin
   5                                 tmp <= registers[`REG_H];
   6                         end
   7                 1:      begin
   8                                 `EXEC_NEWCYCLE;
   9                                 `EXEC_INC_PC;
  10                                 tmp <= registers[`REG_L];
  11                         end
  12                 endcase
  13         end
  14 `endif
  15
  16 `ifdef WRITEBACK
  17         `INSN_LD_SP_HL: begin
  18                 case (cycle)
  19                 0:      registers[`REG_SPH] <= tmp;
  20                 1:      registers[`REG_SPL] <= tmp;
  21                 endcase
  22         end
  23 `endif