1 `define ADDR_NR50 16'hFF24
2 `define ADDR_NR51 16'hFF25
3 `define ADDR_NR52 16'hFF26
11 output reg snd_data_l,
15 reg [7:0] nr50,nr51,nr52;
19 wire [3:0] sndout1,sndout2,sndout3,sndout4;
20 wire [3:0] right_snd =
21 (nr51[0] ? sndout1 : 4'b0) +
22 (nr51[1] ? sndout2 : 4'b0) +
23 (nr51[2] ? sndout3 : 4'b0) +
24 (nr51[3] ? sndout4 : 4'b0);
26 (nr51[4] ? sndout1 : 4'b0) +
27 (nr51[5] ? sndout2 : 4'b0) +
28 (nr51[6] ? sndout3 : 4'b0) +
29 (nr51[7] ? sndout4 : 4'b0);
34 addr == `ADDR_NR50 ? nr50 :
35 addr == `ADDR_NR51 ? nr51 :
36 addr == `ADDR_NR52 ? nr52 : 8'bzzzzzzzz
39 always @ (negedge core_clk) begin
42 `ADDR_NR50: nr50 <= data;
43 `ADDR_NR51: nr51 <= data;
44 `ADDR_NR52: nr52 <= {data[7],7'b1111111};
50 snd_data_l <= (pwmcnt <= left_snd) ? nr50[7] : 0;
51 snd_data_r <= (pwmcnt <= right_snd) ? nr50[3] : 0;