b2c4d35288f8f87897115d36cad85a44418741ea
[fpgaboy.git] / Soundcore.v
1 `define ADDR_NR50 16'hFF24
2 `define ADDR_NR51 16'hFF25
3 `define ADDR_NR52 16'hFF26
4
5 module Soundcore(
6         input core_clk,
7         input wr,
8         input rd,
9         input [15:0] addr,
10         inout [7:0] data,
11         output reg snd_data_l,
12         output reg snd_data_r
13         );
14
15         reg [7:0] nr50,nr51,nr52;
16         reg [3:0] pwmcnt;
17         reg [4:0] cntclk;
18         reg [13:0] lenclk;
19         wire [3:0] sndout1,sndout2,sndout3,sndout4;
20         wire [3:0] right_snd =
21                 (nr51[0] ? sndout1 : 4'b0) +
22                 (nr51[1] ? sndout2 : 4'b0) +
23                 (nr51[2] ? sndout3 : 4'b0) +
24                 (nr51[3] ? sndout4 : 4'b0);
25         wire [3:0] left_snd =
26                 (nr51[4] ? sndout1 : 4'b0) +
27                 (nr51[5] ? sndout2 : 4'b0) +
28                 (nr51[6] ? sndout3 : 4'b0) +
29                 (nr51[7] ? sndout4 : 4'b0);
30         assign sndout3 = 0;
31         assign sndout4 = 0;
32
33         assign data = rd ?
34                          addr == `ADDR_NR50 ? nr50 :
35                          addr == `ADDR_NR51 ? nr51 :
36                          addr == `ADDR_NR52 ? nr52 : 8'bzzzzzzzz
37                       : 8'bzzzzzzzz;
38
39         always @ (negedge core_clk) begin
40                 if(wr) begin
41                         case(addr)
42                         `ADDR_NR50: nr50 <= data;
43                         `ADDR_NR51: nr51 <= data;
44                         `ADDR_NR52: nr52 <= {data[7],7'b1111111};
45                         endcase
46                 end
47                 cntclk <= cntclk + 1;
48                 lenclk <= lenclk + 1;
49                 pwmcnt <= pwmcnt + 1; 
50                 snd_data_l <= (pwmcnt <= left_snd) ? nr50[7] : 0;
51                 snd_data_r <= (pwmcnt <= right_snd) ? nr50[3] : 0;
52         end
53
54         Sound1 s1(
55                 .core_clk(core_clk),
56                 .wr(wr),
57                 .rd(rd),
58                 .addr(addr),
59                 .data(data),
60                 .cntclk(cntclk[4]),
61                 .lenclk(lenclk[13]),
62                 .en(nr52[7]),
63                 .snd_data(sndout1)
64         );
65         
66         Sound2 s2(
67                 .core_clk(core_clk),
68                 .wr(wr),
69                 .rd(rd),
70                 .addr(addr),
71                 .data(data),
72                 .cntclk(cntclk[4]),
73                 .lenclk(lenclk[13]),
74                 .en(nr52[7]),
75                 .snd_data(sndout2)
76         );
77
78 endmodule
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