Move the core to core/
[fpgaboy.git] / System.v
1
2 `timescale 1ns / 1ps
3 module SimROM(
4         input [15:0] address,
5         inout [7:0] data,
6         input clk,
7         input wr, rd);
8
9         reg rdlatch = 0;
10         reg [7:0] odata;
11
12         reg [7:0] rom [32767:0];
13         initial $readmemh("rom.hex", rom);
14
15         wire decode = address[15:13] == 0;
16         always @(posedge clk) begin
17                 rdlatch <= rd && decode;
18                 odata <= rom[address[10:0]];
19         end
20         assign data = rdlatch ? odata : 8'bzzzzzzzz;
21 endmodule
22
23 module BootstrapROM(
24         input [15:0] address,
25         inout [7:0] data,
26         input clk,
27         input wr, rd);
28
29         reg rdlatch = 0;
30         reg [7:0] addrlatch = 0;
31         reg romno = 0, romnotmp = 0;
32         reg [7:0] brom0 [255:0];
33         reg [7:0] brom1 [255:0];
34         
35         initial $readmemh("fpgaboot.hex", brom0);
36         initial $readmemh("gbboot.hex", brom1);
37         
38 `ifdef isim
39         initial romno <= 1;
40 `endif
41
42         wire decode = address[15:8] == 0;
43         wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];
44         always @(posedge clk) begin
45                 rdlatch <= rd && decode;
46                 addrlatch <= address[7:0];
47                 if (wr && decode) romnotmp <= data[0];
48                 if (rd && address == 16'h0000) romno <= romnotmp;       /* Latch when the program restarts. */
49         end
50         assign data = rdlatch ? odata : 8'bzzzzzzzz;
51 endmodule
52
53 module MiniRAM(
54         input [15:0] address,
55         inout [7:0] data,
56         input clk,
57         input wr, rd);
58         
59         reg [7:0] ram [127:0];
60         
61         wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
62         reg rdlatch = 0;
63         reg [7:0] odata;
64         assign data = rdlatch ? odata : 8'bzzzzzzzz;
65         
66         always @(posedge clk)
67         begin
68                 rdlatch <= rd && decode;
69                 if (decode)             // This has to go this way. The only way XST knows how to do
70                 begin                   // block ram is chip select, write enable, and always
71                         if (wr)         // reading. "else if rd" does not cut it ...
72                                 ram[address[6:0]] <= data;
73                         odata <= ram[address[6:0]];
74                 end
75         end
76 endmodule
77
78 module CellularRAM(
79         input clk,
80         input [15:0] address,
81         inout [7:0] data,
82         input wr, rd,
83         output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
84         output wire [22:0] cr_A,
85         inout [15:0] cr_DQ);
86         
87         parameter ADDR_PROGADDRH = 16'hFF60;
88         parameter ADDR_PROGADDRM = 16'hFF61;
89         parameter ADDR_PROGADDRL = 16'hFF62;
90         parameter ADDR_PROGDATA = 16'hFF63;
91         parameter ADDR_MBC = 16'hFF64;
92         
93         reg rdlatch = 0, wrlatch = 0;
94         reg [15:0] addrlatch = 0;
95         reg [7:0] datalatch = 0;
96         
97         reg [7:0] progaddrh, progaddrm, progaddrl;
98         
99         reg [22:0] progaddr;
100         
101         reg [7:0] mbc_emul = 8'b00000101;       // High bit is whether we're poking flash
102                                                 // low 7 bits are the MBC that we are emulating
103         
104         assign cr_nADV = 0;     /* Addresses are always valid! :D */
105         assign cr_nCE = 0;      /* The chip is enabled */
106         assign cr_nLB = 0;      /* Lower byte is enabled */
107         assign cr_nUB = 0;      /* Upper byte is enabled */
108         assign cr_CRE = 0;      /* Data writes, not config */
109         assign cr_CLK = 0;      /* Clock? I think not! */
110         
111         wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA);
112         
113         reg [3:0] rambank = 0;
114         reg [8:0] rombank = 1;
115         
116         assign cr_nOE = decode ? ~rdlatch : 1;
117         assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) || (mbc_emul[6:0] == 0))) ? ~wrlatch : 1;
118         
119         assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
120         assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom, home bank */ {9'b0,addrlatch[13:0]} :
121                         (addrlatch[15:14] == 2'b01) ? /* extrom, paged bank */ {rombank, addrlatch[13:0]} :
122                         (addrlatch[15:13] == 3'b101) ? /* extram */ {1'b1, 5'b0, rambank, addrlatch[12:0]} :
123                         (addrlatch == ADDR_PROGDATA) ? progaddr :
124                         23'b0;
125         
126         always @(posedge clk) begin
127                 case (address)
128                 ADDR_PROGADDRH: if (wr) progaddrh <= data;
129                 ADDR_PROGADDRM: if (wr) progaddrm <= data;
130                 ADDR_PROGADDRL: if (wr) progaddrl <= data;
131                 ADDR_PROGDATA:  if (rd || wr) begin
132                                         progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};
133                                         {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;
134                                 end
135                 ADDR_MBC:       begin
136                                         mbc_emul <= data;
137                                         rambank <= 0;
138                                         rombank <= 1;
139                                 end
140                 endcase
141                 
142                 if (mbc_emul[6:0] == 5) begin
143                         if ((address[15:12] == 4'h2) && wr)
144                                 rombank <= {rombank[8], data};
145                         else if ((address[15:12] == 4'h3) && wr)
146                                 rombank <= {data[0], rombank[7:0]};
147                         else if ((address[15:12] == 4'h4) && wr)
148                                 rambank <= data[3:0];
149                 end
150                 
151                 rdlatch <= rd;
152                 wrlatch <= wr;
153                 addrlatch <= address;
154                 datalatch <= data;
155         end
156         
157         assign data = (rdlatch && decode) ?
158                                 (addrlatch == ADDR_PROGADDRH) ? progaddrh :
159                                 (addrlatch == ADDR_PROGADDRM) ? progaddrm :
160                                 (addrlatch == ADDR_PROGADDRL) ? progaddrl :
161                                 cr_DQ
162                         : 8'bzzzzzzzz;
163 endmodule
164
165 module InternalRAM(
166         input [15:0] address,
167         inout [7:0] data,
168         input clk,
169         input wr, rd);
170         
171         // synthesis attribute ram_style of ram is block
172         reg [7:0] ram [8191:0];
173         
174         wire decode = (address >= 16'hC000) && (address <= 16'hFDFF);   /* This includes echo RAM. */
175         reg [7:0] odata;
176         reg rdlatch = 0;
177         assign data = rdlatch ? odata : 8'bzzzzzzzz;
178         
179         always @(posedge clk)
180         begin
181                 rdlatch <= rd && decode;
182                 if (decode)             // This has to go this way. The only way XST knows how to do
183                 begin                   // block ram is chip select, write enable, and always
184                         if (wr)         // reading. "else if rd" does not cut it ...
185                                 ram[address[12:0]] <= data;
186                         odata <= ram[address[12:0]];
187                 end
188         end
189 endmodule
190
191 module Switches(
192         input [15:0] address,
193         inout [7:0] data,
194         input clk,
195         input wr, rd,
196         input [7:0] switches,
197         output reg [7:0] ledout = 0);
198         
199         wire decode = address == 16'hFF51;
200         reg [7:0] odata;
201         reg rdlatch = 0;
202         assign data = rdlatch ? odata : 8'bzzzzzzzz;
203         
204         always @(posedge clk)
205         begin
206                 rdlatch <= rd && decode;
207                 if (decode && rd)
208                         odata <= switches;
209                 else if (decode && wr)
210                         ledout <= data;
211         end
212 endmodule
213
214 `ifdef isim
215 module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
216 endmodule
217 `endif
218
219 module CoreTop(
220 `ifdef isim
221         output reg vgaclk = 0,
222         output reg clk = 0,
223 `else
224         input xtal,
225         input [7:0] switches,
226         input [3:0] buttons,
227         output wire [7:0] leds,
228         output serio,
229         input serin,
230         output wire [3:0] digits,
231         output wire [7:0] seven,
232         output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
233         output wire [22:0] cr_A,
234         inout [15:0] cr_DQ,
235         input ps2c, ps2d,
236 `endif
237         output wire hs, vs,
238         output wire [2:0] r, g,
239         output wire [1:0] b,
240         output wire soundl, soundr);
241
242 `ifdef isim
243         always #62 clk <= ~clk;
244         always #100 vgaclk <= ~vgaclk;
245         
246         Dumpable dump(r,g,b,hs,vs,vgaclk);
247         
248         wire [7:0] leds;
249         wire serio;
250         wire serin = 1;
251         wire [3:0] digits;
252         wire [7:0] seven;
253         wire [7:0] switches = 8'b0;
254         wire [3:0] buttons = 4'b0;
255 `else   
256         wire xtalb, clk, vgaclk;
257         IBUFG iclkbuf(.O(xtalb), .I(xtal));
258         CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
259         pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
260         wire [7:0] ps2buttons;
261 `endif
262
263         wire [15:0] addr [1:0];
264         wire [7:0] data [1:0];
265         wire wr [1:0], rd [1:0];
266         
267         wire irq, tmrirq, lcdcirq, vblankirq, btnirq;
268         wire [7:0] jaddr;
269         wire [1:0] state;
270         wire ack;
271         
272         GBZ80Core core(
273                 .clk(clk),
274                 .bus0address(addr[0]),
275                 .bus0data(data[0]),
276                 .bus0wr(wr[0]),
277                 .bus0rd(rd[0]),
278                 .bus1address(addr[1]),
279                 .bus1data(data[1]),
280                 .bus1wr(wr[1]),
281                 .bus1rd(rd[1]),
282                 .irq(irq),
283                 .irqack(ack),
284                 .jaddr(jaddr),
285                 .state(state));
286         
287         BootstrapROM brom(
288                 .address(addr[1]),
289                 .data(data[1]),
290                 .clk(clk),
291                 .wr(wr[1]),
292                 .rd(rd[1]));
293         
294 `ifdef isim
295         SimROM rom(
296                 .address(addr[0]),
297                 .data(data[0]),
298                 .clk(clk),
299                 .wr(wr[0]),
300                 .rd(rd[0]));
301 `else
302         CellularRAM cellram(
303                 .address(addr[0]),
304                 .data(data[0]),
305                 .clk(clk),
306                 .wr(wr[0]),
307                 .rd(rd[0]),
308                 .cr_nADV(cr_nADV),
309                 .cr_nCE(cr_nCE),
310                 .cr_nOE(cr_nOE),
311                 .cr_nWE(cr_nWE),
312                 .cr_CRE(cr_CRE),
313                 .cr_nLB(cr_nLB),
314                 .cr_nUB(cr_nUB),
315                 .cr_CLK(cr_CLK),
316                 .cr_A(cr_A),
317                 .cr_DQ(cr_DQ));
318 `endif
319         
320         wire lcdhs, lcdvs, lcdclk;
321         wire [2:0] lcdr, lcdg;
322         wire [1:0] lcdb;
323         
324         LCDC lcdc(
325                 .clk(clk),
326                 .addr(addr[0]),
327                 .data(data[0]),
328                 .wr(wr[0]),
329                 .rd(rd[0]),
330                 .lcdcirq(lcdcirq),
331                 .vblankirq(vblankirq),
332                 .lcdclk(lcdclk),
333                 .lcdhs(lcdhs),
334                 .lcdvs(lcdvs),
335                 .lcdr(lcdr),
336                 .lcdg(lcdg),
337                 .lcdb(lcdb));
338         
339         Framebuffer fb(
340                 .lcdclk(lcdclk),
341                 .lcdhs(lcdhs),
342                 .lcdvs(lcdvs),
343                 .lcdr(lcdr),
344                 .lcdg(lcdg),
345                 .lcdb(lcdb),
346                 .vgaclk(vgaclk),
347                 .vgahs(hs),
348                 .vgavs(vs),
349                 .vgar(r),
350                 .vgag(g),
351                 .vgab(b));
352
353         wire [7:0] sleds;
354 `ifdef isim
355         assign leds = sleds;
356 `else
357         assign leds = sleds | ps2buttons;
358 `endif
359         Switches sw(
360                 .clk(clk),
361                 .address(addr[0]),
362                 .data(data[0]),
363                 .wr(wr[0]),
364                 .rd(rd[0]),
365                 .ledout(sleds),
366                 .switches(switches)
367                 );
368         
369 `ifdef isim
370 `else
371         PS2Button ps2(
372                 .clk(clk),
373                 .inclk(ps2c),
374                 .indata(ps2d),
375                 .buttons(ps2buttons)
376                 );
377 `endif
378         
379         Buttons ass(
380                 .core_clk(clk),
381                 .addr(addr[0]),
382                 .data(data[0]),
383                 .wr(wr[0]),
384                 .rd(rd[0]),
385                 .int(btnirq),
386         `ifdef isim
387                 .buttons(switches)
388         `else
389                 .buttons(ps2buttons)
390         `endif
391                 );
392
393         AddrMon amon(
394                 .clk(clk), 
395                 .addr(addr[0]),
396                 .digit(digits), 
397                 .out(seven),
398                 .freeze(buttons[0]),
399                 .periods(
400                         (state == 2'b00) ? 4'b0010 :
401                         (state == 2'b01) ? 4'b0001 :
402                         (state == 2'b10) ? 4'b1000 :
403                                            4'b0100) );
404          
405         UART nouart (   /* no u */
406                 .clk(clk),
407                 .addr(addr[0]),
408                 .data(data[0]),
409                 .wr(wr[0]),
410                 .rd(rd[0]),
411                 .serial(serio),
412                 .serialrx(serin)
413                 );
414
415         InternalRAM ram(
416                 .clk(clk),
417                 .address(addr[0]),
418                 .data(data[0]),
419                 .wr(wr[0]),
420                 .rd(rd[0])
421                 );
422         
423         MiniRAM mram(
424                 .clk(clk),
425                 .address(addr[1]),
426                 .data(data[1]),
427                 .wr(wr[1]),
428                 .rd(rd[1])
429                 );
430
431         Timer tmr(
432                 .clk(clk),
433                 .addr(addr[0]),
434                 .data(data[0]),
435                 .wr(wr[0]),
436                 .rd(rd[0]),
437                 .irq(tmrirq)
438                 );
439         
440         Interrupt intr(
441                 .clk(clk),
442                 .addr(addr[0]),
443                 .data(data[0]),
444                 .wr(wr[0]),
445                 .rd(rd[0]),
446                 .vblank(vblankirq),
447                 .lcdc(lcdcirq),
448                 .tovf(tmrirq),
449                 .serial(1'b0),
450                 .buttons(btnirq),
451                 .master(irq),
452                 .ack(ack),
453                 .jaddr(jaddr));
454         
455         Soundcore sound(
456                 .core_clk(clk),
457                 .addr(addr[0]),
458                 .data(data[0]),
459                 .rd(rd[0]),
460                 .wr(wr[0]),
461                 .snd_data_l(soundl),
462                 .snd_data_r(soundr));
463 endmodule
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