]> Joshua Wise's Git repositories - fpgaboy.git/blob - core/insn_vop_intr.v
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[fpgaboy.git] / core / insn_vop_intr.v
1 `ifdef EXECUTE
2         `INSN_VOP_INTR: begin
3                 case (cycle)
4                 0:      `EXEC_WRITE(`_SP - 1, `_PCH)
5                 1:      `EXEC_WRITE(`_SP - 2, `_PCL)
6                 2:      begin
7                                 irqack <= 1;
8                                 `EXEC_NEWCYCLE
9                         end
10                 endcase
11         end
12 `endif
13
14 `ifdef WRITEBACK
15         `INSN_VOP_INTR: begin
16                 case (cycle)
17                 0:      begin end
18                 1:      begin end
19                 2:      begin
20                                 ie <= 0;
21                                 `_PC <= {8'b0, jaddr};
22                                 irqack <= 0;    // Must be at the same time as we latch jaddr, or we race!
23                                 `_SP <= `_SP - 2;
24                         end
25                 endcase
26         end
27 `endif
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