core/insn_incdec_reg8.v

   1 `define INSN_INCDEC_reg8        9'b000xxx10x
   2
   3 `ifdef EXECUTE
   4         `INSN_INCDEC_reg8: begin
   5                 `EXEC_INC_PC
   6                 `EXEC_NEWCYCLE
   7                 case (opcode[5:3])
   8                 `INSN_reg_A:    tmp <= `_A;
   9                 `INSN_reg_B:    tmp <= `_B;
  10                 `INSN_reg_C:    tmp <= `_C;
  11                 `INSN_reg_D:    tmp <= `_D;
  12                 `INSN_reg_E:    tmp <= `_E;
  13                 `INSN_reg_H:    tmp <= `_H;
  14                 `INSN_reg_L:    tmp <= `_L;
  15                 endcase
  16         end
  17 `endif
  18
  19 `ifdef WRITEBACK
  20         `INSN_INCDEC_reg8: begin
  21                 case (opcode[5:3])
  22                 `INSN_reg_A:    `_A <= tmp + (opcode[0] ? 8'hFF : 8'h01);
  23                 `INSN_reg_B:    `_B <= tmp + (opcode[0] ? 8'hFF : 8'h01);
  24                 `INSN_reg_C:    `_C <= tmp + (opcode[0] ? 8'hFF : 8'h01);
  25                 `INSN_reg_D:    `_D <= tmp + (opcode[0] ? 8'hFF : 8'h01);
  26                 `INSN_reg_E:    `_E <= tmp + (opcode[0] ? 8'hFF : 8'h01);
  27                 `INSN_reg_H:    `_H <= tmp + (opcode[0] ? 8'hFF : 8'h01);
  28                 `INSN_reg_L:    `_L <= tmp + (opcode[0] ? 8'hFF : 8'h01);
  29                 endcase
  30                 `_F <= {
  31                                 ((tmp + (opcode[0] ? 8'hFF : 8'h01)) == 8'h00) ? 1'b1 : 1'b0,
  32                                 1'b0,
  33                                 (({1'b0,tmp[3:0]} + (opcode[0] ? 5'h1F : 5'h01)) >> 4) ? 1'b1 : 1'b0,
  34                                 `_F[4:0]};
  35         end
  36 `endif