]> Joshua Wise's Git repositories - fpgaboy.git/blob - core/insn_rst.v
Fix ADD HL,xx.
[fpgaboy.git] / core / insn_rst.v
1 `define INSN_RST                9'b011xxx111
2
3 `ifdef EXECUTE
4         `INSN_RST: begin
5                 case (cycle)
6                 0:      `EXEC_INC_PC            // This goes FIRST in RST
7                 1:      `EXEC_WRITE(`_SP - 1, `_PCH)
8                 2:      `EXEC_WRITE(`_SP - 2, `_PCL)
9                 3:      begin
10                                 `EXEC_NEWCYCLE
11                                 `_PC <= {10'b0,opcode[5:3],3'b0};
12                         end
13                 endcase
14         end
15 `endif
16
17 `ifdef WRITEBACK
18         `INSN_RST: begin
19                 case (cycle)
20                 0:      begin /* type F */ end
21                 1:      begin /* type F */ end
22                 2:      begin /* type F */ end
23                 3:      `_SP <= `_SP - 2;
24                 endcase
25         end
26 `endif
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