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[fpgaboy.git] / insn_incdec_reg8.v
1 `ifdef EXECUTE
2         `INSN_INCDEC_reg8: begin
3                 `EXEC_INC_PC
4                 `EXEC_NEWCYCLE
5                 case (opcode[5:3])
6                 `INSN_reg_A:    tmp <= `_A;
7                 `INSN_reg_B:    tmp <= `_B;
8                 `INSN_reg_C:    tmp <= `_C;
9                 `INSN_reg_D:    tmp <= `_D;
10                 `INSN_reg_E:    tmp <= `_E;
11                 `INSN_reg_H:    tmp <= `_H;
12                 `INSN_reg_L:    tmp <= `_L;
13                 endcase
14         end
15 `endif
16
17 `ifdef WRITEBACK
18         `INSN_INCDEC_reg8: begin
19                 case (opcode[5:3])
20                 `INSN_reg_A:    `_A <= tmp + (opcode[0] ? 8'hFF : 8'h01);
21                 `INSN_reg_B:    `_B <= tmp + (opcode[0] ? 8'hFF : 8'h01);
22                 `INSN_reg_C:    `_C <= tmp + (opcode[0] ? 8'hFF : 8'h01);
23                 `INSN_reg_D:    `_D <= tmp + (opcode[0] ? 8'hFF : 8'h01);
24                 `INSN_reg_E:    `_E <= tmp + (opcode[0] ? 8'hFF : 8'h01);
25                 `INSN_reg_H:    `_H <= tmp + (opcode[0] ? 8'hFF : 8'h01);
26                 `INSN_reg_L:    `_L <= tmp + (opcode[0] ? 8'hFF : 8'h01);
27                 endcase
28                 `_F <= {
29                                 (tmp + (opcode[0] ? 8'hFF : 8'h01)) ? 1'b0 : 1'b1,
30                                 1'b0,
31                                 (({1'b0,tmp[3:0]} + (opcode[0] ? 5'h1F : 5'h01)) >> 4) ? 1'b1 : 1'b0,
32                                 `_F[4:0]};
33         end
34 `endif
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