]> Joshua Wise's Git repositories - fpgaboy.git/blob - core/insn_ld_reg_imm16.v
Fix add sp, imm8 *sweatdrop*
[fpgaboy.git] / core / insn_ld_reg_imm16.v
1 `define INSN_LD_reg_imm16       9'b000xx0001
2
3 `ifdef EXECUTE
4         `INSN_LD_reg_imm16: begin
5                 `EXEC_INC_PC
6                 case (cycle)
7                 0:      `EXEC_READ(`_PC + 1)
8                 1:      `EXEC_READ(`_PC + 1)
9                 2:      `EXEC_NEWCYCLE
10                 endcase
11         end
12 `endif
13
14 `ifdef WRITEBACK
15         `INSN_LD_reg_imm16: begin
16                 case (cycle)
17                 0:      begin /* */ end
18                 1:      begin
19                                 case (opcode[5:4])
20                                 `INSN_reg16_BC: `_C <= rdata;
21                                 `INSN_reg16_DE: `_E <= rdata;
22                                 `INSN_reg16_HL: `_L <= rdata;
23                                 `INSN_reg16_SP: `_SPL <= rdata;
24                                 endcase
25                         end
26                 2:      begin
27                                 case (opcode[5:4])
28                                 `INSN_reg16_BC: `_B <= rdata;
29                                 `INSN_reg16_DE: `_D <= rdata;
30                                 `INSN_reg16_HL: `_H <= rdata;
31                                 `INSN_reg16_SP: `_SPH <= rdata;
32                                 endcase
33                         end
34                 endcase
35         end
36 `endif
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