86154433f0322641cfea4e00bbb5cc51e5b3f369
[fpgaboy.git] / LCDC.v
1 `define ADDR_LCDC       16'hFF40
2 `define ADDR_STAT       16'hFF41
3 `define ADDR_SCY        16'hFF42
4 `define ADDR_SCX        16'hFF43
5 `define ADDR_LY         16'hFF44
6 `define ADDR_LYC        16'hFF45
7 `define ADDR_DMA        16'hFF46
8 `define ADDR_BGP        16'hFF47
9 `define ADDR_OBP0       16'hFF48
10 `define ADDR_OBP1       16'hFF49
11 `define ADDR_WY         16'hFF4A
12 `define ADDR_WX         16'hFF4B
13
14 module LCDC(
15         input [15:0] addr,
16         inout [7:0] data,
17         input clk,      // 8MHz clock
18         input wr, rd,
19         output wire lcdcirq,
20         output wire vblankirq,
21         output wire lcdclk, lcdvs, lcdhs,
22         output reg [2:0] lcdr, lcdg, output reg [1:0] lcdb);
23         
24         /***** Needed prototypes *****/
25         wire [1:0] pixdata;
26         
27         /***** Internal clock that is stable and does not depend on CPU in single/double clock mode *****/
28         reg clk4 = 0;
29         always @(posedge clk)
30                 clk4 = ~clk4;
31         
32         /***** LCD control registers *****/
33         reg [7:0] rLCDC = 8'h00;
34         reg [7:0] rSTAT = 8'h00;
35         reg [7:0] rSCY = 8'b00;
36         reg [7:0] rSCX = 8'b00;
37         reg [7:0] rLYC = 8'b00;
38         reg [7:0] rDMA = 8'b00;
39         reg [7:0] rBGP = 8'b00;
40         reg [7:0] rOBP0 = 8'b00;
41         reg [7:0] rOBP1 = 8'b00;
42         reg [7:0] rWY = 8'b00;
43         reg [7:0] rWX = 8'b00;
44         
45         /***** Sync generation *****/
46         
47         /* A complete cycle takes 456 clocks.
48          * VBlank lasts 4560 clocks (10 scanlines) -- LY = 144 - 153.
49          *
50          * Modes: 0 -> in hblank and OAM/VRAM available - present 207 clks
51          *        1 -> in vblank and OAM/VRAM available
52          *        2 -> OAM in use - present 86 clks
53          *        3 -> OAM/VRAM in use - present 163 clks
54          * So, X = 0~162 is HActive,
55          * X = 163-369 is HBlank,
56          * X = 370-455 is HWhirrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr.
57          * [02:15:10] <Judge_> LY is updated near the 0 -> 2 transition
58          * [02:15:38] <Judge_> it seems to be updated internally first before it is visible in the LY register itself
59          * [02:15:40] <Judge_> some kind of delay
60          * [02:16:19] <Judge_> iirc it is updated about 4 cycles prior to mode 2
61          */
62         reg [8:0] posx = 9'h000;
63         reg [7:0] posy = 8'h00;
64         
65         wire vraminuse = (posx < 163) && (posy < 144) && rLCDC[7];
66         wire oaminuse = (posx > 369) && (posy < 144) && rLCDC[7];
67         
68         wire display = (posx > 2) && (posx < 163) && (posy < 144);
69         
70         wire [1:0] mode = (posy < 144) ?
71                                 (vraminuse ? 2'b11 :
72                                  oaminuse ? 2'b10 :
73                                  2'b00)
74                                 : 2'b01;
75         
76         wire [7:0] vxpos = rSCX + posx - 3;
77         wire [7:0] vypos = rSCY + posy;
78         
79         assign lcdvs = (posy == 153) && (posx == 2) && rLCDC[7];
80         assign lcdhs = (posx == 2) && rLCDC[7];
81         assign lcdclk = clk4 && rLCDC[7];
82         
83         wire [2:0] lcdr_ = display ? {pixdata[1] ? 3'b111 : 3'b000} : 3'b000;
84         wire [2:0] lcdg_ = display ? {pixdata[0] ? 3'b111 : 3'b000} : 3'b000;
85         wire [1:0] lcdb_ = display ? {(vypos < 8 || vxpos < 8) ? 2'b11 : 2'b00} : 2'b00;
86         
87         reg mode00irq = 0, mode01irq = 0, mode10irq = 0, lycirq = 0;
88         assign lcdcirq = (rSTAT[3] & mode00irq) | (rSTAT[4] & mode01irq) | (rSTAT[5] & mode10irq) | (rSTAT[6] & lycirq);
89         assign vblankirq = (posx == 0 && posy == 153);
90         
91         always @(posedge clk4)
92         begin
93                 if (posx == 455) begin
94                         posx <= 0;
95                         if (posy == 153) begin
96                                 posy <= 0;
97                                 if (0 == rLYC)
98                                         lycirq <= 1;
99                         end else begin
100                                 posy <= posy + 1;
101                                 /* Check for vblank and generate an IRQ if needed. */
102                                 if (posy == 143) begin 
103                                         mode01irq <= 1;
104                                 end
105                                 if ((posy + 1) == rLYC)
106                                         lycirq <= 1;
107                                 
108                         end
109                 end else begin
110                         posx <= posx + 1;
111                         if (posx == 165)
112                                 mode00irq <= 1;
113                         else if (posx == 373)
114                                 mode10irq <= 1;
115                         else begin
116                                 mode00irq <= 0;
117                                 mode01irq <= 0;
118                                 mode10irq <= 0;
119                         end
120                         lycirq <= 0;
121                 end
122                 
123                 lcdr <= lcdr_;
124                 lcdg <= lcdg_;
125                 lcdb <= lcdb_;
126         end
127         
128         /***** Video RAM *****/
129         /* Base is 0x8000
130          *
131          * Tile data from 8000-8FFF or 8800-97FF
132          * Background tile maps 9800-9BFF or 9C00-9FFF
133          */
134         reg [7:0] tiledatahigh [3071:0];
135         reg [7:0] tiledatalow [3071:0];
136         reg [7:0] bgmap1 [1023:0];
137         reg [7:0] bgmap2 [1023:0];
138         
139         // Upper five bits are Y coord, lower five bits are X coord
140         // The new tile number is loaded when vxpos[2:0] is 3'b110
141         // The new tile data is loaded when vxpos[2:0] is 3'b111
142         // The new tile data is latched and ready when vxpos[2:0] is 3'b000!
143         wire [7:0] vxpos_ = vxpos + 1;
144         wire [9:0] bgmapaddr = {vypos[7:3], vxpos_[7:3]};
145         reg [7:0] tileno;
146         wire [10:0] tileaddr = {tileno, vypos[2:0]};
147         reg [7:0] tilehigh, tilelow;
148         assign pixdata = {tilehigh[7-vxpos[2:0]], tilelow[7-vxpos[2:0]]};
149         
150         wire decode_tiledata = (addr >= 16'h8000) && (addr <= 16'h97FF);
151         wire decode_bgmap1 = (addr >= 16'h9800) && (addr <= 16'h9BFF);
152
153         wire [9:0] bgmapaddr_in = vraminuse ? bgmapaddr : addr[9:0];
154         wire [11:0] tileaddr_in = vraminuse ? tileaddr : addr[12:1];
155         
156         always @(negedge clk)
157                 if ((vraminuse && ((posx == 2) || (vxpos[2:0] == 3'b111))) || decode_bgmap1) begin
158                         tileno <= bgmap1[bgmapaddr_in];
159                         if (wr && decode_bgmap1 && ~vraminuse)
160                                 bgmap1[bgmapaddr_in] <= data;
161                 end
162         
163         always @(negedge clk)
164                 if ((vraminuse && ((posx == 3) || (vxpos[2:0] == 3'b000))) || decode_tiledata) begin
165                         tilehigh <= tiledatahigh[tileaddr_in];
166                         tilelow <= tiledatalow[tileaddr_in];
167                         if (wr && addr[0] && decode_tiledata && ~vraminuse)
168                                 tiledatahigh[tileaddr_in] <= data;
169                         if (wr && ~addr[0] && decode_tiledata && ~vraminuse)
170                                 tiledatalow[tileaddr_in] <= data;
171                 end
172   
173         /***** Bus interface *****/
174         assign data = rd ?
175                         ((addr == `ADDR_LCDC) ? rLCDC :
176                          (addr == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} :
177                          (addr == `ADDR_SCY) ? rSCY :
178                          (addr == `ADDR_SCX) ? rSCX :
179                          (addr == `ADDR_LY) ? posy :
180                          (addr == `ADDR_LYC) ? rLYC :
181                          (addr == `ADDR_BGP) ? rBGP :
182                          (addr == `ADDR_OBP0) ? rOBP0 :
183                          (addr == `ADDR_OBP1) ? rOBP1 :
184                          (addr == `ADDR_WY) ? rWY :
185                          (addr == `ADDR_WX) ? rWX :
186                          (decode_tiledata && addr[0]) ? tilehigh :
187                          (decode_tiledata && ~addr[0]) ? tilelow :
188                          (decode_bgmap1) ? tileno :
189                          8'bzzzzzzzz) :
190                 8'bzzzzzzzz;
191   
192         always @(negedge clk)
193         begin
194                 if (wr)
195                         case (addr)
196                         `ADDR_LCDC:     rLCDC <= data;
197                         `ADDR_STAT:     rSTAT <= {data[7:2],rSTAT[1:0]};
198                         `ADDR_SCY:      rSCY <= data;
199                         `ADDR_SCX:      rSCX <= data;
200                         `ADDR_LYC:      rLYC <= data;
201                         `ADDR_DMA:      rDMA <= data;
202                         `ADDR_BGP:      rBGP <= data;
203                         `ADDR_OBP0:     rOBP0 <= data;
204                         `ADDR_OBP1:     rOBP1 <= data;
205                         `ADDR_WY:       rWY <= data;
206                         `ADDR_WX:       rWX <= data;
207                         endcase
208         end
209 endmodule
This page took 0.023431 seconds and 2 git commands to generate.