84b33b78315fd2e623d52b769e39c3e00d0579de
[fpgaboy.git] / System.v
1 `timescale 1ns / 1ps
2
3 module SimROM(
4         input [15:0] address,
5         inout [7:0] data,
6         input clk,
7         input wr, rd);
8
9         reg rdlatch = 0;
10         reg [7:0] odata;
11
12         reg [7:0] rom [32767:0];
13         initial $readmemh("rom.hex", rom);
14
15         wire decode = address[15:13] == 0;
16         always @(posedge clk) begin
17                 rdlatch <= rd && decode;
18                 odata <= rom[address[10:0]];
19         end
20         assign data = rdlatch ? odata : 8'bzzzzzzzz;
21 endmodule
22
23 module BootstrapROM(
24         input [15:0] address,
25         inout [7:0] data,
26         input clk,
27         input wr, rd);
28
29         reg rdlatch = 0;
30         reg [7:0] addrlatch = 0;
31         reg romno = 0, romnotmp = 0;
32         reg [7:0] brom0 [255:0];
33         reg [7:0] brom1 [255:0];
34         
35         initial $readmemh("fpgaboot.hex", brom0);
36         initial $readmemh("gbboot.hex", brom1);
37         
38 `ifdef isim
39         initial romno <= 1;
40 `endif
41
42         wire decode = address[15:8] == 0;
43         wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];
44         always @(posedge clk) begin
45                 rdlatch <= rd && decode;
46                 addrlatch <= address[7:0];
47                 if (wr && decode) romnotmp <= data[0];
48                 if (rd && address == 16'h0000) romno <= romnotmp;       /* Latch when the program restarts. */
49         end
50         assign data = rdlatch ? odata : 8'bzzzzzzzz;
51 endmodule
52
53 module MiniRAM(
54         input [15:0] address,
55         inout [7:0] data,
56         input clk,
57         input wr, rd);
58         
59         reg [7:0] ram [127:0];
60         
61         wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
62         reg rdlatch = 0;
63         reg [7:0] odata;
64         assign data = rdlatch ? odata : 8'bzzzzzzzz;
65         
66         always @(posedge clk)
67         begin
68                 rdlatch <= rd && decode;
69                 if (decode)             // This has to go this way. The only way XST knows how to do
70                 begin                   // block ram is chip select, write enable, and always
71                         if (wr)         // reading. "else if rd" does not cut it ...
72                                 ram[address[6:0]] <= data;
73                         odata <= ram[address[6:0]];
74                 end
75         end
76 endmodule
77
78 module CellularRAM(
79         input clk,
80         input [15:0] address,
81         inout [7:0] data,
82         input wr, rd,
83         output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
84         output wire st_nCE, st_nRST,
85         output wire [22:0] cr_A,
86         inout [15:0] cr_DQ);
87         
88         parameter ADDR_PROGADDRH = 16'hFF60;
89         parameter ADDR_PROGADDRM = 16'hFF61;
90         parameter ADDR_PROGADDRL = 16'hFF62;
91         parameter ADDR_PROGDATA = 16'hFF63;
92         parameter ADDR_PROGFLASH = 16'hFF65;
93         parameter ADDR_MBC = 16'hFF64;
94         
95         reg rdlatch = 0, wrlatch = 0;
96         reg [15:0] addrlatch = 0;
97         reg [7:0] datalatch = 0;
98         
99         reg [7:0] progaddrh, progaddrm, progaddrl;
100         
101         reg [22:0] progaddr;
102         
103         reg [7:0] mbc_emul = 8'b00000101;       // High bit is whether we're poking flash
104                                                 // low 7 bits are the MBC that we are emulating
105         
106         assign cr_nADV = 0;     /* Addresses are always valid! :D */
107         assign cr_nCE = ~(addrlatch != ADDR_PROGFLASH); /* The chip is enabled */
108         assign cr_nLB = 0;      /* Lower byte is enabled */
109         assign cr_nUB = 0;      /* Upper byte is enabled */
110         assign cr_CRE = 0;      /* Data writes, not config */
111         assign cr_CLK = 0;      /* Clock? I think not! */
112         
113         assign st_nRST = 1;     /* Keep the strataflash out of reset. */
114         assign st_nCE = ~(addrlatch == ADDR_PROGFLASH);
115         
116         wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH);
117         
118         reg [3:0] rambank = 0;
119         reg [8:0] rombank = 1;
120         
121         assign cr_nOE = decode ? ~rdlatch : 1;
122         assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH) || (mbc_emul[6:0] == 0) || (addrlatch[15:13] == 3'b101))) ? ~wrlatch : 1;
123         
124         assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
125         assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom, home bank */ {9'b0,addrlatch[13:0]} :
126                         (addrlatch[15:14] == 2'b01) ? /* extrom, paged bank */ {rombank, addrlatch[13:0]} :
127                         (addrlatch[15:13] == 3'b101) ? /* extram */ {1'b1, 5'b0, rambank, addrlatch[12:0]} :
128                         ((addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH)) ? progaddr :
129                         23'b0;
130         
131         always @(posedge clk) begin
132                 case (address)
133                 ADDR_PROGADDRH: if (wr) progaddrh <= data;
134                 ADDR_PROGADDRM: if (wr) progaddrm <= data;
135                 ADDR_PROGADDRL: if (wr) progaddrl <= data;
136                 ADDR_PROGDATA:  if (rd || wr) begin
137                                         progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};
138                                         {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;
139                                 end
140                 ADDR_PROGFLASH: if (rd || wr) begin
141                                         progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};
142                                         {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;
143                                 end
144                 ADDR_MBC:       begin
145                                         mbc_emul <= data;
146                                         rambank <= 0;
147                                         rombank <= 1;
148                                 end
149                 endcase
150                 
151                 if (mbc_emul[6:0] == 5) begin
152                         if ((address[15:12] == 4'h2) && wr)
153                                 rombank <= {rombank[8], data};
154                         else if ((address[15:12] == 4'h3) && wr)
155                                 rombank <= {data[0], rombank[7:0]};
156                         else if ((address[15:12] == 4'h4) && wr)
157                                 rambank <= data[3:0];
158                 end
159                 
160                 rdlatch <= rd;
161                 wrlatch <= wr;
162                 addrlatch <= address;
163                 datalatch <= data;
164         end
165         
166         assign data = (rdlatch && decode) ?
167                                 (addrlatch == ADDR_PROGADDRH) ? progaddrh :
168                                 (addrlatch == ADDR_PROGADDRM) ? progaddrm :
169                                 (addrlatch == ADDR_PROGADDRL) ? progaddrl :
170                                 cr_DQ
171                         : 8'bzzzzzzzz;
172 endmodule
173
174 module InternalRAM(
175         input [15:0] address,
176         inout [7:0] data,
177         input clk,
178         input wr, rd);
179         
180         // synthesis attribute ram_style of ram is block
181         reg [7:0] ram [8191:0];
182         
183         wire decode = (address >= 16'hC000) && (address <= 16'hFDFF);   /* This includes echo RAM. */
184         reg [7:0] odata;
185         reg rdlatch = 0;
186         assign data = rdlatch ? odata : 8'bzzzzzzzz;
187         
188         always @(posedge clk)
189         begin
190                 rdlatch <= rd && decode;
191                 if (decode)             // This has to go this way. The only way XST knows how to do
192                 begin                   // block ram is chip select, write enable, and always
193                         if (wr)         // reading. "else if rd" does not cut it ...
194                                 ram[address[12:0]] <= data;
195                         odata <= ram[address[12:0]];
196                 end
197         end
198 endmodule
199
200 module Switches(
201         input [15:0] address,
202         inout [7:0] data,
203         input clk,
204         input wr, rd,
205         input [7:0] switches,
206         output reg [7:0] ledout = 0);
207         
208         wire decode = address == 16'hFF51;
209         reg [7:0] odata;
210         reg rdlatch = 0;
211         assign data = rdlatch ? odata : 8'bzzzzzzzz;
212         
213         always @(posedge clk)
214         begin
215                 rdlatch <= rd && decode;
216                 if (decode && rd)
217                         odata <= switches;
218                 else if (decode && wr)
219                         ledout <= data;
220         end
221 endmodule
222
223 `ifdef isim
224 module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
225 endmodule
226 `endif
227
228 module CoreTop(
229 `ifdef isim
230         output reg vgaclk = 0,
231         output reg clk = 0,
232 `else
233         input xtal,
234         input [7:0] switches,
235         input [3:0] buttons,
236         output wire [7:0] leds,
237         output serio,
238         input serin,
239         output wire [3:0] digits,
240         output wire [7:0] seven,
241         output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK, st_nCE, st_nRST,
242         output wire [22:0] cr_A,
243         inout [15:0] cr_DQ,
244         input ps2c, ps2d,
245         output txp, txm,
246 `endif
247         output wire hs, vs,
248         output wire [2:0] r, g,
249         output wire [1:0] b,
250         output wire soundl, soundr);
251
252 `ifdef isim
253         always #62 clk <= ~clk;
254         always #100 vgaclk <= ~vgaclk;
255         
256         Dumpable dump(r,g,b,hs,vs,vgaclk);
257         
258         wire [7:0] leds;
259         wire serio;
260         wire serin = 1;
261         wire [3:0] digits;
262         wire [7:0] seven;
263         wire [7:0] switches = 8'b0;
264         wire [3:0] buttons = 4'b0;
265 `else   
266         wire xtalb, clk, vgaclk, ethclk;
267         IBUFG iclkbuf(.O(xtalb), .I(xtal));
268         CPUDCM cpudcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
269         pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
270         ethDCM ethdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(ethclk));
271         wire [7:0] ps2buttons;
272 `endif
273
274         wire [15:0] addr [1:0];
275         wire [7:0] data [1:0];
276         wire wr [1:0], rd [1:0];
277         
278         wire irq, tmrirq, lcdcirq, vblankirq, btnirq;
279         wire [7:0] jaddr;
280         wire [1:0] state;
281         wire ack;
282         
283         GBZ80Core core(
284                 .clk(clk),
285                 .bus0address(addr[0]),
286                 .bus0data(data[0]),
287                 .bus0wr(wr[0]),
288                 .bus0rd(rd[0]),
289                 .bus1address(addr[1]),
290                 .bus1data(data[1]),
291                 .bus1wr(wr[1]),
292                 .bus1rd(rd[1]),
293                 .irq(irq),
294                 .irqack(ack),
295                 .jaddr(jaddr),
296                 .state(state));
297         
298         BootstrapROM brom(
299                 .address(addr[1]),
300                 .data(data[1]),
301                 .clk(clk),
302                 .wr(wr[1]),
303                 .rd(rd[1]));
304         
305 `ifdef isim
306         SimROM rom(
307                 .address(addr[0]),
308                 .data(data[0]),
309                 .clk(clk),
310                 .wr(wr[0]),
311                 .rd(rd[0]));
312 `else
313         CellularRAM cellram(
314                 .address(addr[0]),
315                 .data(data[0]),
316                 .clk(clk),
317                 .wr(wr[0]),
318                 .rd(rd[0]),
319                 .cr_nADV(cr_nADV),
320                 .cr_nCE(cr_nCE),
321                 .cr_nOE(cr_nOE),
322                 .cr_nWE(cr_nWE),
323                 .cr_CRE(cr_CRE),
324                 .cr_nLB(cr_nLB),
325                 .cr_nUB(cr_nUB),
326                 .cr_CLK(cr_CLK),
327                 .cr_A(cr_A),
328                 .cr_DQ(cr_DQ),
329                 .st_nCE(st_nCE),
330                 .st_nRST(st_nRST));
331 `endif
332         
333         wire lcdhs, lcdvs, lcdclk;
334         wire [2:0] lcdr, lcdg;
335         wire [1:0] lcdb;
336         
337         LCDC lcdc(
338                 .clk(clk),
339                 .addr(addr[0]),
340                 .data(data[0]),
341                 .wr(wr[0]),
342                 .rd(rd[0]),
343                 .lcdcirq(lcdcirq),
344                 .vblankirq(vblankirq),
345                 .lcdclk(lcdclk),
346                 .lcdhs(lcdhs),
347                 .lcdvs(lcdvs),
348                 .lcdr(lcdr),
349                 .lcdg(lcdg),
350                 .lcdb(lcdb));
351         
352         Framebuffer fb(
353                 .lcdclk(lcdclk),
354                 .lcdhs(lcdhs),
355                 .lcdvs(lcdvs),
356                 .lcdr(lcdr),
357                 .lcdg(lcdg),
358                 .lcdb(lcdb),
359                 .vgaclk(vgaclk),
360                 .vgahs(hs),
361                 .vgavs(vs),
362                 .vgar(r),
363                 .vgag(g),
364                 .vgab(b));
365
366         wire [7:0] sleds;
367 `ifdef isim
368         assign leds = sleds;
369 `else
370         assign leds = sleds | ps2buttons;
371 `endif
372         Switches sw(
373                 .clk(clk),
374                 .address(addr[0]),
375                 .data(data[0]),
376                 .wr(wr[0]),
377                 .rd(rd[0]),
378                 .ledout(sleds),
379                 .switches(switches)
380                 );
381         
382 `ifdef isim
383 `else
384         PS2Button ps2(
385                 .clk(clk),
386                 .inclk(ps2c),
387                 .indata(ps2d),
388                 .buttons(ps2buttons)
389                 );
390 `endif
391         
392         Buttons ass(
393                 .core_clk(clk),
394                 .addr(addr[0]),
395                 .data(data[0]),
396                 .wr(wr[0]),
397                 .rd(rd[0]),
398                 .int(btnirq),
399         `ifdef isim
400                 .buttons(switches)
401         `else
402                 .buttons(ps2buttons)
403         `endif
404                 );
405
406         AddrMon amon(
407                 .clk(clk), 
408                 .addr(addr[0]),
409                 .digit(digits), 
410                 .out(seven),
411                 .freeze(buttons[0]),
412                 .periods(
413                         (state == 2'b00) ? 4'b0010 :
414                         (state == 2'b01) ? 4'b0001 :
415                         (state == 2'b10) ? 4'b1000 :
416                                            4'b0100) );
417          
418         UART nouart (   /* no u */
419                 .clk(clk),
420                 .addr(addr[0]),
421                 .data(data[0]),
422                 .wr(wr[0]),
423                 .rd(rd[0]),
424                 .serial(serio),
425                 .serialrx(serin)
426                 );
427
428         InternalRAM ram(
429                 .clk(clk),
430                 .address(addr[0]),
431                 .data(data[0]),
432                 .wr(wr[0]),
433                 .rd(rd[0])
434                 );
435         
436         MiniRAM mram(
437                 .clk(clk),
438                 .address(addr[1]),
439                 .data(data[1]),
440                 .wr(wr[1]),
441                 .rd(rd[1])
442                 );
443
444         Timer tmr(
445                 .clk(clk),
446                 .addr(addr[0]),
447                 .data(data[0]),
448                 .wr(wr[0]),
449                 .rd(rd[0]),
450                 .irq(tmrirq)
451                 );
452         
453         Interrupt intr(
454                 .clk(clk),
455                 .addr(addr[0]),
456                 .data(data[0]),
457                 .wr(wr[0]),
458                 .rd(rd[0]),
459                 .vblank(vblankirq),
460                 .lcdc(lcdcirq),
461                 .tovf(tmrirq),
462                 .serial(1'b0),
463                 .buttons(btnirq),
464                 .master(irq),
465                 .ack(ack),
466                 .jaddr(jaddr));
467         
468         Soundcore sound(
469                 .core_clk(clk),
470                 .addr(addr[0]),
471                 .data(data[0]),
472                 .rd(rd[0]),
473                 .wr(wr[0]),
474                 .snd_data_l(soundl),
475                 .snd_data_r(soundr));
476
477 `ifdef isim
478 `else   
479         Ethernet eth(
480                 .clk(clk),
481                 .wr(wr[0]),
482                 .rd(rd[0]),
483                 .addr(addr[0]),
484                 .data(data[0]),
485                 .ethclk(ethclk),
486                 .txp(txp),
487                 .txm(txm));
488 `endif
489 endmodule
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