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[fpgaboy.git] / insn_jr-jrcc.v
1 `ifdef EXECUTE
2         `INSN_JR_imm,`INSN_JRCC_imm: begin
3                 case (cycle)
4                 0:      begin
5                                 `EXEC_INC_PC;
6                                 `EXEC_NEXTADDR_PCINC;
7                                 rd <= 1;
8                         end
9                 1: begin
10                                 `EXEC_INC_PC;
11                                 if (opcode[5]) begin    // i.e., JP cc,nn
12                                         /* We need to check the condition code to bail out. */
13                                         case (opcode[4:3])
14                                         `INSN_cc_NZ:    if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
15                                         `INSN_cc_Z:             if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
16                                         `INSN_cc_NC:    if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
17                                         `INSN_cc_C:             if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
18                                         endcase
19                                 end
20                         end
21                 2:      begin
22                                 `EXEC_NEWCYCLE;
23                         end
24                 endcase
25         end
26 `endif
27
28 `ifdef WRITEBACK
29         `INSN_JR_imm,`INSN_JRCC_imm: begin
30                 case (cycle)
31                 0:      begin /* type F */ end
32                 1:      tmp <= rdata;
33                 2:      {registers[`REG_PCH],registers[`REG_PCL]} <=
34                                 {registers[`REG_PCH],registers[`REG_PCL]} +
35                                 {tmp[7]?8'hFF:8'h00,tmp};
36                 endcase
37         end
38 `endif
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