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[fpgaboy.git] / insn_ld_reg_imm8.v
1 `ifdef EXECUTE
2         `INSN_LD_reg_imm8: begin
3                 case (cycle)
4                 0:      begin
5                                 `EXEC_INC_PC;
6                                 `EXEC_NEXTADDR_PCINC;
7                                 rd <= 1;
8                         end
9                 1:      begin
10                                 `EXEC_INC_PC;
11                                 if (opcode[5:3] == `INSN_reg_dHL) begin
12                                         address <= {registers[`REG_H], registers[`REG_L]};
13                                         wdata <= rdata;
14                                         rd <= 0;
15                                         wr <= 1;
16                                 end else begin
17                                         `EXEC_NEWCYCLE;
18                                 end
19                         end
20                 2:      begin
21                                 `EXEC_NEWCYCLE;
22                         end
23                 endcase
24         end
25 `endif
26
27 `ifdef WRITEBACK
28         `INSN_LD_reg_imm8:
29                 case (cycle)
30                 0:      begin end
31                 1:      case (opcode[5:3])
32                         `INSN_reg_A:    begin registers[`REG_A] <= rdata; end
33                         `INSN_reg_B:    begin registers[`REG_B] <= rdata; end
34                         `INSN_reg_C:    begin registers[`REG_C] <= rdata; end
35                         `INSN_reg_D:    begin registers[`REG_D] <= rdata; end
36                         `INSN_reg_E:    begin registers[`REG_E] <= rdata; end
37                         `INSN_reg_H:    begin registers[`REG_H] <= rdata; end
38                         `INSN_reg_L:    begin registers[`REG_L] <= rdata; end
39                         `INSN_reg_dHL:  begin /* Go off to cycle 2 */ end
40                         endcase
41                 2:      begin end
42                 endcase
43 `endif
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