]> Joshua Wise's Git repositories - fpgaboy.git/blob - insn_rst.v
Add cut 1 of a cellram module
[fpgaboy.git] / insn_rst.v
1 `ifdef EXECUTE
2         `INSN_RST: begin
3                 case (cycle)
4                 0:      `EXEC_INC_PC            // This goes FIRST in RST
5                 1:      `EXEC_WRITE(`_SP - 1, `_PCH)
6                 2:      `EXEC_WRITE(`_SP - 2, `_PCL)
7                 3:      begin
8                                 `EXEC_NEWCYCLE
9                                 `_PC <= {10'b0,opcode[5:3],3'b0};
10                         end
11                 endcase
12         end
13 `endif
14
15 `ifdef WRITEBACK
16         `INSN_RST: begin
17                 case (cycle)
18                 0:      begin /* type F */ end
19                 1:      begin /* type F */ end
20                 2:      begin /* type F */ end
21                 3:      `_SP <= `_SP - 2;
22                 endcase
23         end
24 `endif
This page took 0.028533 seconds and 4 git commands to generate.