62683d3bbd5b2b69809da5f0ec33b112f08a054d
[fpgaboy.git] / System.v
1
2 `timescale 1ns / 1ps
3 module ROM(
4         input [15:0] address,
5         inout [7:0] data,
6         input clk,
7         input wr, rd);
8
9         reg rdlatch = 0;
10         reg [7:0] odata;
11
12         // synthesis attribute ram_style of rom is block
13         reg [7:0] rom [1023:0];
14         initial $readmemh("rom.hex", rom);
15
16         wire decode = address[15:13] == 0;
17         always @(posedge clk) begin
18                 rdlatch <= rd && decode;
19                 odata <= rom[address[10:0]];
20         end
21         assign data = rdlatch ? odata : 8'bzzzzzzzz;
22 endmodule
23
24 module BootstrapROM(
25         input [15:0] address,
26         inout [7:0] data,
27         input clk,
28         input wr, rd);
29
30         reg rdlatch = 0;
31         reg [7:0] addrlatch = 0;
32         reg romno = 0, romnotmp = 0;
33         reg [7:0] brom0 [255:0];
34         reg [7:0] brom1 [255:0];
35         
36         initial $readmemh("fpgaboot.hex", brom0);
37         initial $readmemh("gbboot.hex", brom1);
38
39         wire decode = address[15:8] == 0;
40         wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];
41         always @(posedge clk) begin
42                 rdlatch <= rd && decode;
43                 addrlatch <= address[7:0];
44                 if (wr && decode) romnotmp <= data[0];
45                 if (rd && address == 16'h0000) romno <= romnotmp;       /* Latch when the program restarts. */
46         end
47         assign data = rdlatch ? odata : 8'bzzzzzzzz;
48 endmodule
49
50 module MiniRAM(
51         input [15:0] address,
52         inout [7:0] data,
53         input clk,
54         input wr, rd);
55         
56         reg [7:0] ram [127:0];
57         
58         wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
59         reg rdlatch = 0;
60         reg [7:0] odata;
61         assign data = rdlatch ? odata : 8'bzzzzzzzz;
62         
63         always @(posedge clk)
64         begin
65                 rdlatch <= rd && decode;
66                 if (decode)             // This has to go this way. The only way XST knows how to do
67                 begin                   // block ram is chip select, write enable, and always
68                         if (wr)         // reading. "else if rd" does not cut it ...
69                                 ram[address[6:0]] <= data;
70                         odata <= ram[address[6:0]];
71                 end
72         end
73 endmodule
74
75 module CellularRAM(
76         input clk,
77         input [15:0] address,
78         inout [7:0] data,
79         input wr, rd,
80         output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
81         output wire [22:0] cr_A,
82         inout [15:0] cr_DQ);
83         
84         parameter ADDR_PROGADDRH = 16'hFF60;
85         parameter ADDR_PROGADDRM = 16'hFF61;
86         parameter ADDR_PROGADDRL = 16'hFF62;
87         parameter ADDR_PROGDATA = 16'hFF63;
88         
89         reg rdlatch = 0, wrlatch = 0;
90         reg [15:0] addrlatch = 0;
91         reg [7:0] datalatch = 0;
92         
93         reg [7:0] progaddrh, progaddrm, progaddrl;
94         
95         reg [22:0] progaddr;
96         
97         assign cr_nADV = 0;     /* Addresses are always valid! :D */
98         assign cr_nCE = 0;      /* The chip is enabled */
99         assign cr_nLB = 0;      /* Lower byte is enabled */
100         assign cr_nUB = 0;      /* Upper byte is enabled */
101         assign cr_CRE = 0;      /* Data writes, not config */
102         assign cr_CLK = 0;      /* Clock? I think not! */
103         
104         wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA);
105         
106         assign cr_nOE = decode ? ~rdlatch : 1;
107         assign cr_nWE = decode ? ~wrlatch : 1;
108         
109         assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
110         assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom */ {9'b0,addrlatch[13:0]} :
111                         (addrlatch[15:13] == 3'b101) ? {1'b1, 9'b0, addrlatch[12:0]} :
112                         (addrlatch == ADDR_PROGDATA) ? progaddr :
113                         23'b0;
114         
115         reg [7:0] regbuf;
116         
117         always @(posedge clk) begin
118                 case (address)
119                 ADDR_PROGADDRH: if (wr) progaddrh <= data;
120                 ADDR_PROGADDRM: if (wr) progaddrm <= data;
121                 ADDR_PROGADDRL: if (wr) progaddrl <= data;
122                 ADDR_PROGDATA:  if (rd || wr) begin
123                                         progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddr[7:0]};
124                                         {progaddrh[6:0], progaddrm[7:0], progaddr[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddr[7:0]} + 23'b1;
125                                 end
126                 endcase
127                 rdlatch <= rd;
128                 wrlatch <= wr;
129                 addrlatch <= address;
130                 datalatch <= data;
131         end
132         
133         assign data = (rdlatch && decode) ?
134                                 (addrlatch == ADDR_PROGADDRH) ? progaddrh :
135                                 (addrlatch == ADDR_PROGADDRM) ? progaddrm :
136                                 (addrlatch == ADDR_PROGADDRL) ? progaddrl :
137                                 cr_DQ
138                         : 8'bzzzzzzzz;
139 endmodule
140
141 module InternalRAM(
142         input [15:0] address,
143         inout [7:0] data,
144         input clk,
145         input wr, rd);
146         
147         // synthesis attribute ram_style of ram is block
148         reg [7:0] ram [8191:0];
149         
150         wire decode = (address >= 16'hC000) && (address <= 16'hFDFF);   /* This includes echo RAM. */
151         reg [7:0] odata;
152         reg rdlatch = 0;
153         assign data = rdlatch ? odata : 8'bzzzzzzzz;
154         
155         always @(posedge clk)
156         begin
157                 rdlatch <= rd && decode;
158                 if (decode)             // This has to go this way. The only way XST knows how to do
159                 begin                   // block ram is chip select, write enable, and always
160                         if (wr)         // reading. "else if rd" does not cut it ...
161                                 ram[address[12:0]] <= data;
162                         odata <= ram[address[12:0]];
163                 end
164         end
165 endmodule
166
167 module Switches(
168         input [15:0] address,
169         inout [7:0] data,
170         input clk,
171         input wr, rd,
172         input [7:0] switches,
173         output reg [7:0] ledout = 0);
174         
175         wire decode = address == 16'hFF51;
176         reg [7:0] odata;
177         reg rdlatch = 0;
178         assign data = rdlatch ? odata : 8'bzzzzzzzz;
179         
180         always @(posedge clk)
181         begin
182                 rdlatch <= rd && decode;
183                 if (decode && rd)
184                         odata <= switches;
185                 else if (decode && wr)
186                         ledout <= data;
187         end
188 endmodule
189
190 `ifdef isim
191 module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
192 endmodule
193 `endif
194
195 module CoreTop(
196 `ifdef isim
197         output reg vgaclk = 0,
198         output reg clk = 0,
199 `else
200         input xtal,
201         input [7:0] switches,
202         input [3:0] buttons,
203         output wire [7:0] leds,
204         output serio,
205         output wire [3:0] digits,
206         output wire [7:0] seven,
207         output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
208         output wire [22:0] cr_A,
209         inout [15:0] cr_DQ,
210 `endif
211         output wire hs, vs,
212         output wire [2:0] r, g,
213         output wire [1:0] b,
214         output wire soundl, soundr);
215
216 `ifdef isim
217         always #62 clk <= ~clk;
218         always #100 vgaclk <= ~vgaclk;
219         
220         Dumpable dump(r,g,b,hs,vs,vgaclk);
221         
222         wire [7:0] leds;
223         wire serio;
224         wire [3:0] digits;
225         wire [7:0] seven;
226         wire [7:0] switches = 8'b0;
227         wire [3:0] buttons = 4'b0;
228 `else   
229         wire xtalb, clk, vgaclk;
230         IBUFG iclkbuf(.O(xtalb), .I(xtal));
231         CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
232         pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
233 `endif
234
235         wire [15:0] addr [1:0];
236         wire [7:0] data [1:0];
237         wire wr [1:0], rd [1:0];
238         
239         wire irq, tmrirq, lcdcirq, vblankirq;
240         wire [7:0] jaddr;
241         wire [1:0] state;
242         
243         GBZ80Core core(
244                 .clk(clk),
245                 .bus0address(addr[0]),
246                 .bus0data(data[0]),
247                 .bus0wr(wr[0]),
248                 .bus0rd(rd[0]),
249                 .bus1address(addr[1]),
250                 .bus1data(data[1]),
251                 .bus1wr(wr[1]),
252                 .bus1rd(rd[1]),
253                 .irq(irq),
254                 .jaddr(jaddr),
255                 .state(state));
256         
257         BootstrapROM brom(
258                 .address(addr[1]),
259                 .data(data[1]),
260                 .clk(clk),
261                 .wr(wr[1]),
262                 .rd(rd[1]));
263         
264 `ifdef isim
265         ROM rom(
266                 .address(addr[0]),
267                 .data(data[0]),
268                 .clk(clk),
269                 .wr(wr[0]),
270                 .rd(rd[0]));
271 `else
272         CellularRAM cellram(
273                 .address(addr[0]),
274                 .data(data[0]),
275                 .clk(clk),
276                 .wr(wr[0]),
277                 .rd(rd[0]),
278                 .cr_nADV(cr_nADV),
279                 .cr_nCE(cr_nCE),
280                 .cr_nOE(cr_nOE),
281                 .cr_nWE(cr_nWE),
282                 .cr_CRE(cr_CRE),
283                 .cr_nLB(cr_nLB),
284                 .cr_nUB(cr_nUB),
285                 .cr_CLK(cr_CLK),
286                 .cr_A(cr_A),
287                 .cr_DQ(cr_DQ));
288 `endif
289         
290         wire lcdhs, lcdvs, lcdclk;
291         wire [2:0] lcdr, lcdg;
292         wire [1:0] lcdb;
293         
294         LCDC lcdc(
295                 .clk(clk),
296                 .addr(addr[0]),
297                 .data(data[0]),
298                 .wr(wr[0]),
299                 .rd(rd[0]),
300                 .lcdcirq(lcdcirq),
301                 .vblankirq(vblankirq),
302                 .lcdclk(lcdclk),
303                 .lcdhs(lcdhs),
304                 .lcdvs(lcdvs),
305                 .lcdr(lcdr),
306                 .lcdg(lcdg),
307                 .lcdb(lcdb));
308         
309         Framebuffer fb(
310                 .lcdclk(lcdclk),
311                 .lcdhs(lcdhs),
312                 .lcdvs(lcdvs),
313                 .lcdr(lcdr),
314                 .lcdg(lcdg),
315                 .lcdb(lcdb),
316                 .vgaclk(vgaclk),
317                 .vgahs(hs),
318                 .vgavs(vs),
319                 .vgar(r),
320                 .vgag(g),
321                 .vgab(b));
322         
323         AddrMon amon(
324                 .clk(clk), 
325                 .addr(addr[0]),
326                 .digit(digits), 
327                 .out(seven),
328                 .freeze(buttons[0]),
329                 .periods(
330                         (state == 2'b00) ? 4'b0010 :
331                         (state == 2'b01) ? 4'b0001 :
332                         (state == 2'b10) ? 4'b1000 :
333                                            4'b0100) );
334          
335         Switches sw(
336                 .clk(clk),
337                 .address(addr[0]),
338                 .data(data[0]),
339                 .wr(wr[0]),
340                 .rd(rd[0]),
341                 .ledout(leds),
342                 .switches(switches)
343                 );
344
345         UART nouart (   /* no u */
346                 .clk(clk),
347                 .addr(addr[0]),
348                 .data(data[0]),
349                 .wr(wr[0]),
350                 .rd(rd[0]),
351                 .serial(serio)
352                 );
353
354         InternalRAM ram(
355                 .clk(clk),
356                 .address(addr[0]),
357                 .data(data[0]),
358                 .wr(wr[0]),
359                 .rd(rd[0])
360                 );
361         
362         MiniRAM mram(
363                 .clk(clk),
364                 .address(addr[1]),
365                 .data(data[1]),
366                 .wr(wr[1]),
367                 .rd(rd[1])
368                 );
369
370         Timer tmr(
371                 .clk(clk),
372                 .addr(addr[0]),
373                 .data(data[0]),
374                 .wr(wr[0]),
375                 .rd(rd[0]),
376                 .irq(tmrirq)
377                 );
378         
379         Interrupt intr(
380                 .clk(clk),
381                 .addr(addr[0]),
382                 .data(data[0]),
383                 .wr(wr[0]),
384                 .rd(rd[0]),
385                 .vblank(vblankirq),
386                 .lcdc(lcdcirq),
387                 .tovf(tmrirq),
388                 .serial(1'b0),
389                 .buttons(1'b0),
390                 .master(irq),
391                 .jaddr(jaddr));
392         
393         Soundcore sound(
394                 .core_clk(clk),
395                 .addr(addr[0]),
396                 .data(data[0]),
397                 .rd(rd[0]),
398                 .wr(wr[0]),
399                 .snd_data_l(soundl),
400                 .snd_data_r(soundr));
401 endmodule
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