LCDC.v

   1 `define ADDR_LCDC       16'hFF40
   2 `define ADDR_STAT       16'hFF41
   3 `define ADDR_SCY        16'hFF42
   4 `define ADDR_SCX        16'hFF43
   5 `define ADDR_LY         16'hFF44
   6 `define ADDR_LYC        16'hFF45
   7 `define ADDR_DMA        16'hFF46
   8 `define ADDR_BGP        16'hFF47
   9 `define ADDR_OBP0       16'hFF48
  10 `define ADDR_OBP1       16'hFF49
  11 `define ADDR_WY         16'hFF4A
  12 `define ADDR_WX         16'hFF4B
  13
  14 module LCDC(
  15         input [15:0] addr,
  16         inout [7:0] data,
  17         input clk,      // 8MHz clock
  18         input wr, rd,
  19         output wire lcdcirq,
  20         output wire vblankirq,
  21         output wire vgavs, vgahs,
  22         output wire [2:0] vgar, vgag, output wire [1:0] vgab);
  23
  24         /***** Internal clock that is stable and does not depend on CPU in single/double clock mode *****/
  25         reg clk4 = 0;
  26         always @(posedge clk)
  27                 clk4 = ~clk4;
  28
  29         /***** LCD control registers *****/
  30         reg [7:0] rLCDC = 8'h91;
  31         reg [7:0] rSTAT = 8'h00;
  32         reg [7:0] rSCY = 8'b00;
  33         reg [7:0] rSCX = 8'b00;
  34         reg [7:0] rLYC = 8'b00;
  35         reg [7:0] rDMA = 8'b00;
  36         reg [7:0] rBGP = 8'b00;
  37         reg [7:0] rOBP0 = 8'b00;
  38         reg [7:0] rOBP1 = 8'b00;
  39         reg [7:0] rWY = 8'b00;
  40         reg [7:0] rWX = 8'b00;
  41
  42         /***** Sync generation *****/
  43
  44         /* A complete cycle takes 456 clocks.
  45          * VBlank lasts 4560 clocks (10 scanlines) -- LY = 144 - 153.
  46          *
  47          * Modes: 0 -> in hblank and OAM/VRAM available - present 207 clks
  48          *        1 -> in vblank and OAM/VRAM available
  49          *        2 -> OAM in use - present 83 clks
  50          *        3 -> OAM/VRAM in use - present 166 clks
  51          * So, X = 0~165 is HActive,
  52          * X = 166-372 is HBlank,
  53          * X = 373-455 is HWhirrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr.
  54          */
  55         reg [8:0] posx = 9'h000;
  56         reg [7:0] posy = 8'h00;
  57         wire [1:0] mode = (posy < 144) ?
  58                                 ((posx < 166) ? 2'b11 :
  59                                  (posx < 373) ? 2'b00 :
  60                                  2'b10)
  61                                 : 2'b01;
  62
  63         assign vgavs = (posy > 147) && (posy < 151);
  64         assign vgahs = (posx < 250) && (posx < 350);
  65         assign vgar = (posx < 160) && (posy < 144) ? {posy == rLYC ? 3'b111 : 3'b000} : 3'b000;
  66         assign vgag = (posx < 160) && (posy < 144) ? {posy < rSCY ? 3'b111 : 3'b000} : 3'b000;
  67         assign vgab = (posx < 160) && (posy < 144) ? {2'b11} : 2'b00;
  68
  69         reg mode00irq = 0, mode01irq = 0, mode10irq = 0, lycirq = 0;
  70         assign lcdcirq = (rSTAT[3] & mode00irq) | (rSTAT[4] & mode01irq) | (rSTAT[5] & mode10irq) | (rSTAT[6] & lycirq);
  71         assign vblankirq = (posx == 0 && posy == 153);
  72
  73         always @(posedge clk4)
  74         begin
  75                 if (posx == 455) begin
  76                         posx <= 0;
  77                         if (posy == 153) begin
  78                                 posy <= 0;
  79                                 if (0 == rLYC)
  80                                         lycirq <= 1;
  81                         end else begin
  82                                 posy <= posy + 1;
  83                                 /* Check for vblank and generate an IRQ if needed. */
  84                                 if (posy == 143) begin
  85                                         mode01irq <= 1;
  86                                 end
  87                                 if ((posy + 1) == rLYC)
  88                                         lycirq <= 1;
  89
  90                         end
  91                 end else begin
  92                         posx <= posx + 1;
  93                         if (posx == 165)
  94                                 mode00irq <= 1;
  95                         else if (posx == 373)
  96                                 mode10irq <= 1;
  97                         else begin
  98                                 mode00irq <= 0;
  99                                 mode01irq <= 0;
 100                                 mode10irq <= 0;
 101                         end
 102                         lycirq <= 0;
 103                 end
 104
 105         end
 106
 107         /***** Bus interface *****/
 108         assign data = rd ?
 109                         (addr == `ADDR_LCDC) ? rLCDC :
 110                         (addr == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} :
 111                         (addr == `ADDR_SCY) ? rSCY :
 112                         (addr == `ADDR_SCX) ? rSCX :
 113                         (addr == `ADDR_LY) ? posy :
 114                         (addr == `ADDR_LYC) ? rLYC :
 115                         (addr == `ADDR_BGP) ? rBGP :
 116                         (addr == `ADDR_OBP0) ? rOBP0 :
 117                         (addr == `ADDR_OBP1) ? rOBP1 :
 118                         (addr == `ADDR_WY) ? rWY :
 119                         (addr == `ADDR_WX) ? rWX :
 120                         8'bzzzzzzzz :
 121                 8'bzzzzzzzz;
 122
 123         always @(negedge clk)
 124         begin
 125                 if (wr)
 126                         case (addr)
 127                         `ADDR_LCDC:     rLCDC <= data;
 128                         `ADDR_STAT:     rSTAT <= {data[7:2],rSTAT[1:0]};
 129                         `ADDR_SCY:      rSCY <= data;
 130                         `ADDR_SCX:      rSCX <= data;
 131                         `ADDR_LYC:      rLYC <= data;
 132                         `ADDR_DMA:      rDMA <= data;
 133                         `ADDR_BGP:      rBGP <= data;
 134                         `ADDR_OBP0:     rOBP0 <= data;
 135                         `ADDR_OBP1:     rOBP1 <= data;
 136                         `ADDR_WY:       rWY <= data;
 137                         `ADDR_WX:       rWX <= data;
 138                         endcase
 139         end
 140 endmodule