1 `define ADDR_DIV 16'hFF04
2 `define ADDR_TIMA 16'hFF05
3 `define ADDR_TMA 16'hFF06
4 `define ADDR_TAC 16'hFF07
15 reg [15:0] addrlatch = 0;
16 reg [7:0] tima = 0, tma = 0, tac = 0, div = 0;
20 wire is_tima = addrlatch == `ADDR_TIMA;
21 wire is_tma = addrlatch == `ADDR_TMA;
22 wire is_tac = addrlatch == `ADDR_TAC;
24 assign data = rdlatch ?
32 (tac[1:0] == 2'b00) ? (clkdv == 10'b0) :
33 (tac[1:0] == 2'b01) ? (clkdv[3:0] == 4'b0) :
34 (tac[1:0] == 2'b10) ? (clkdv[5:0] == 6'b0) :
35 (clkdv[7:0] == 8'b0) :
38 always @ (posedge clk)
45 `ADDR_DIV: div <= 8'b0;
46 `ADDR_TIMA: tima <= data;
47 `ADDR_TMA: tma <= data;
48 `ADDR_TAC: tac <= data;
59 {ovf,tima} <= {1'b0,tima} + 1;
64 if(clkdv[7:0] == 8'b0)