]> Joshua Wise's Git repositories - fpgaboy.git/blob - core/insn_ldm8_a.v
RAM needs to be writable, I guess
[fpgaboy.git] / core / insn_ldm8_a.v
1 `define INSN_LD8M_A             9'b0111x0000    // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
2
3 // If opcode[4], then ld A, x, else ld x, A
4 // If opcode[1], then ld 16m8, else ld 8m8
5
6 `ifdef EXECUTE
7         `INSN_LD8M_A: begin
8                 case (cycle)
9                 0:      begin
10                                 `EXEC_INC_PC
11                                 `EXEC_READ(`_PC + 16'h0001)
12                         end
13                 1:      if (opcode[4])  // LD A,x
14                                 `EXEC_READ(({8'hFF, rdata}))
15                         else
16                                 `EXEC_WRITE(({8'hFF, rdata}), `_A)
17                 2:      begin
18                                 `EXEC_NEWCYCLE
19                                 `EXEC_INC_PC
20                         end
21                 endcase
22         end
23 `endif
24
25 `ifdef WRITEBACK
26         `INSN_LD8M_A: begin
27                 case (cycle)
28                 0:      begin end
29                 1:      begin end
30                 2:      if (opcode[4]) `_A <= rdata;
31                 endcase
32         end
33 `endif
34
This page took 0.03063 seconds and 4 git commands to generate.