added butans
[fpgaboy.git] / Buttons.v
1 `define ADDR_P1 16'hFF10
2
3 /* note: buttons are 'pressed' when the input is high */
4
5 module Buttons(
6         input core_clk,
7         input wr,
8         input rd,
9         input [15:0] addr,
10         inout [7:0] data,
11         input [7:0] buttons
12         output reg int
13         );
14
15         reg [7:0] p1;
16         reg [3:0] oldp1013;
17
18         assign data = (rd && (addr == `ADDR_P1)) ? p1 : 8'bzzzzzzzz;
19
20         wire p1013 = (p1[4] ? 4'b1111 : ~buttons[3:0]) | (p1[5] ? 4'b1111 : ~buttons[7:4]);
21
22         always @ (negedge core_clk) begin
23                 if(wr) begin
24                         case(addr)
25                         `ADDR_P1: p1[5:4] <= data[5:4];
26                         endcase
27                 end
28                 p1[3:0] <= p1013;
29                 oldp1013 <= p1013;
30                 int <= | (oldp1013 & (oldp1013 ^ p1013));
31         end
32 endmodule
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