Sound1.v

   1 `define ADDR_NR10 16'hFF10
   2 `define ADDR_NR11 16'hFF11
   3 `define ADDR_NR12 16'hFF12
   4 `define ADDR_NR13 16'hFF13
   5 `define ADDR_NR14 16'hFF14
   6
   7 module Sound1(
   8         input core_clk,
   9         input wr,
  10         input rd,
  11         input [15:0] addr,
  12         inout [7:0] data,
  13         input cntclk,
  14         input lenclk,
  15         input en,
  16         output [3:0] snd_data
  17         );
  18
  19         /* can be optimized as register file */
  20         reg [7:0] nr10 = 0, nr11 = 0, nr12 = 0, nr13 = 0, nr14 = 0;
  21         reg [10:0] counter = 0;
  22         reg [4:0] lencnt = 0;
  23         reg [3:0] delta = 4'b1111;
  24         reg toggle = 0;
  25         reg [3:0] snd_out = 0;
  26
  27         reg rdlatch;
  28         reg [15:0] addrlatch;
  29
  30         assign snd_data = en ? snd_out : 0;
  31
  32         assign data = rdlatch ?
  33                          addrlatch == `ADDR_NR10 ? nr10 :
  34                          addrlatch == `ADDR_NR11 ? nr11 :
  35                          addrlatch == `ADDR_NR12 ? nr12 :
  36                          addrlatch == `ADDR_NR13 ? nr13 :
  37                          addrlatch == `ADDR_NR14 ? nr14 : 8'bzzzzzzzz
  38                       : 8'bzzzzzzzz;
  39
  40         always @ (posedge core_clk) begin
  41                 rdlatch <= rd;
  42                 addrlatch <= addr;
  43                 if(en && wr) begin
  44                         case(addr)
  45                         `ADDR_NR10: nr10 <= data;
  46                         `ADDR_NR11: nr11 <= data;
  47                         `ADDR_NR12: nr12 <= data;
  48                         `ADDR_NR13: nr13 <= data;
  49                         `ADDR_NR14: nr14 <= data;
  50                         endcase
  51                 end
  52                 else if(!en) begin
  53                         nr10 <= 8'h80;
  54                         nr11 <= 8'h3F;
  55                         nr12 <= 8'h00;
  56                         nr13 <= 8'hFF;
  57                         nr14 <= 8'hBF;
  58                 end
  59         end
  60
  61         always @ (posedge cntclk) begin
  62                 if(counter)
  63                         counter <= counter - 1;
  64                 else begin
  65                         counter <= ~{nr14[2:0],nr13} + 1;  /* possible A */
  66                         toggle <= ~toggle;
  67                 end
  68
  69                 snd_out <= toggle ? delta : 0;  /* Leave it to Dennis. */
  70         end
  71
  72         always @ (posedge lenclk) begin
  73                 if(lencnt)
  74                         lencnt <= lencnt - 1;            /* possible A */
  75                 else
  76                         lencnt <= ~nr11[4:0] + 1;
  77         end
  78
  79 endmodule