GBZ80Core.v

   1 `define REG_A   0
   2 `define REG_B   1
   3 `define REG_C   2
   4 `define REG_D   3
   5 `define REG_E   4
   6 `define REG_F   5
   7 `define REG_H   6
   8 `define REG_L   7
   9 `define REG_SPH 8
  10 `define REG_SPL 9
  11 `define REG_PCH 10
  12 `define REG_PCL 11
  13
  14 `define _A      registers[`REG_A]
  15 `define _B      registers[`REG_B]
  16 `define _C      registers[`REG_C]
  17 `define _D      registers[`REG_D]
  18 `define _E      registers[`REG_E]
  19 `define _F      registers[`REG_F]
  20 `define _H      registers[`REG_H]
  21 `define _L      registers[`REG_L]
  22 `define _SPH    registers[`REG_SPH]
  23 `define _SPL    registers[`REG_SPL]
  24 `define _PCH    registers[`REG_PCH]
  25 `define _PCL    registers[`REG_PCL]
  26 `define _AF     {`_A, `_F}
  27 `define _BC     {`_B, `_C}
  28 `define _DE     {`_D, `_E}
  29 `define _HL     {`_H, `_L}
  30 `define _SP     {`_SPH, `_SPL}
  31 `define _PC     {`_PCH, `_PCL}
  32
  33 `define FLAG_Z  8'b10000000
  34 `define FLAG_N  8'b01000000
  35 `define FLAG_H  8'b00100000
  36 `define FLAG_C  8'b00010000
  37
  38 `define STATE_FETCH             2'h0
  39 `define STATE_DECODE            2'h1
  40 `define STATE_EXECUTE           2'h2
  41 `define STATE_WRITEBACK         2'h3
  42
  43 `define INSN_LD_reg_imm8        8'b00xxx110
  44 `define INSN_HALT               8'b01110110
  45 `define INSN_LD_HL_reg          8'b01110xxx
  46 `define INSN_LD_reg_HL          8'b01xxx110
  47 `define INSN_LD_reg_reg         8'b01xxxxxx
  48 `define INSN_LD_reg_imm16       8'b00xx0001
  49 `define INSN_LD_SP_HL           8'b11111001
  50 `define INSN_PUSH_reg           8'b11xx0101
  51 `define INSN_POP_reg            8'b11xx0001
  52 `define INSN_LDH_AC             8'b111x0010     // Either LDH A,(C) or LDH (C),A
  53 `define INSN_LDx_AHL            8'b001xx010     // LDD/LDI A,(HL) / (HL),A
  54 `define INSN_ALU8               8'b10xxxxxx     // 10 xxx yyy
  55 `define INSN_ALU8IMM            8'b11xxx110
  56 `define INSN_NOP                8'b00000000
  57 `define INSN_RST                8'b11xxx111
  58 `define INSN_RET                8'b110x1001     // 1 = RETI, 0 = RET
  59 `define INSN_RETCC              8'b110xx000
  60 `define INSN_CALL               8'b11001101
  61 `define INSN_CALLCC             8'b110xx100     // Not that call/cc.
  62 `define INSN_JP_imm             8'b11000011
  63 `define INSN_JPCC_imm           8'b110xx010
  64 `define INSN_ALU_A              8'b00xxx111
  65 `define INSN_JP_HL              8'b11101001
  66 `define INSN_JR_imm             8'b00011000
  67 `define INSN_JRCC_imm           8'b001xx000
  68 `define INSN_INCDEC16           8'b00xxx011
  69 `define INSN_VOP_INTR           8'b11111100     // 0xFC is grabbed by the fetch if there is an interrupt pending.
  70 `define INSN_DI                 8'b11110011
  71 `define INSN_EI                 8'b11111011
  72 `define INSN_INCDEC_HL          8'b0011010x
  73 `define INSN_INCDEC_reg8        8'b00xxx10x
  74
  75 `define INSN_cc_NZ              2'b00
  76 `define INSN_cc_Z               2'b01
  77 `define INSN_cc_NC              2'b10
  78 `define INSN_cc_C               2'b11
  79
  80 `define INSN_reg_A              3'b111
  81 `define INSN_reg_B              3'b000
  82 `define INSN_reg_C              3'b001
  83 `define INSN_reg_D              3'b010
  84 `define INSN_reg_E              3'b011
  85 `define INSN_reg_H              3'b100
  86 `define INSN_reg_L              3'b101
  87 `define INSN_reg_dHL            3'b110
  88 `define INSN_reg16_BC           2'b00
  89 `define INSN_reg16_DE           2'b01
  90 `define INSN_reg16_HL           2'b10
  91 `define INSN_reg16_SP           2'b11
  92 `define INSN_stack_AF           2'b11
  93 `define INSN_stack_BC           2'b00
  94 `define INSN_stack_DE           2'b01
  95 `define INSN_stack_HL           2'b10
  96 `define INSN_alu_ADD            3'b000
  97 `define INSN_alu_ADC            3'b001
  98 `define INSN_alu_SUB            3'b010
  99 `define INSN_alu_SBC            3'b011
 100 `define INSN_alu_AND            3'b100
 101 `define INSN_alu_XOR            3'b101
 102 `define INSN_alu_OR             3'b110
 103 `define INSN_alu_CP             3'b111          // Oh lawd, is dat some CP?
 104 `define INSN_alu_RLCA           3'b000
 105 `define INSN_alu_RRCA           3'b001
 106 `define INSN_alu_RLA            3'b010
 107 `define INSN_alu_RRA            3'b011
 108 `define INSN_alu_DAA            3'b100
 109 `define INSN_alu_CPL            3'b101
 110 `define INSN_alu_SCF            3'b110
 111 `define INSN_alu_CCF            3'b111
 112
 113 `define EXEC_INC_PC             `_PC <= `_PC + 1;
 114 `define EXEC_NEXTADDR_PCINC     address <= `_PC + 1;
 115 `define EXEC_NEWCYCLE           begin newcycle <= 1; rd <= 1; wr <= 0; end
 116 `define EXEC_WRITE(ad, da)      begin address <= (ad); wdata <= (da); wr <= 1; end end
 117 `define EXEC_READ(ad)           begin address <= (ad); rd <= 1; end end
 118
 119 module GBZ80Core(
 120         input clk,
 121         output reg [15:0] busaddress,   /* BUS_* is latched on STATE_FETCH. */
 122         inout [7:0] busdata,
 123         output reg buswr, output reg busrd,
 124         input irq, input [7:0] jaddr,
 125         output reg [1:0] state);
 126
 127 //      reg [1:0] state;                                        /* State within this bus cycle (see STATE_*). */
 128         reg [2:0] cycle;                                        /* Cycle for instructions. */
 129
 130         reg [7:0] registers[11:0];
 131
 132         reg [15:0] address;                             /* Address for the next bus operation. */
 133
 134         reg [7:0] opcode;                               /* Opcode from the current machine cycle. */
 135
 136         reg [7:0] rdata, wdata;         /* Read data from this bus cycle, or write data for the next. */
 137         reg rd, wr, newcycle;
 138
 139         reg [7:0] tmp, tmp2;                    /* Generic temporary regs. */
 140
 141         reg [7:0] buswdata;
 142         assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
 143
 144         reg ie, iedelay;
 145
 146         initial begin
 147                 registers[ 0] <= 0;
 148                 registers[ 1] <= 0;
 149                 registers[ 2] <= 0;
 150                 registers[ 3] <= 0;
 151                 registers[ 4] <= 0;
 152                 registers[ 5] <= 0;
 153                 registers[ 6] <= 0;
 154                 registers[ 7] <= 0;
 155                 registers[ 8] <= 0;
 156                 registers[ 9] <= 0;
 157                 registers[10] <= 0;
 158                 registers[11] <= 0;
 159                 rd <= 1;
 160                 wr <= 0;
 161                 newcycle <= 1;
 162                 state <= 0;
 163                 cycle <= 0;
 164                 busrd <= 0;
 165                 buswr <= 0;
 166                 busaddress <= 0;
 167                 ie <= 0;
 168                 iedelay <= 0;
 169                 opcode <= 0;
 170                 state <= `STATE_WRITEBACK;
 171                 cycle <= 0;
 172         end
 173
 174         always @(posedge clk)
 175                 case (state)
 176                 `STATE_FETCH: begin
 177                         if (newcycle) begin
 178                                 busaddress <= {registers[`REG_PCH], registers[`REG_PCL]};
 179                                 buswr <= 0;
 180                                 busrd <= 1;
 181                         end else begin
 182                                 busaddress <= address;
 183                                 buswr <= wr;
 184                                 busrd <= rd;
 185                                 if (wr)
 186                                         buswdata <= wdata;
 187                         end
 188                         state <= `STATE_DECODE;
 189                 end
 190                 `STATE_DECODE: begin
 191                         if (newcycle) begin
 192                                 if (ie && irq)
 193                                         opcode <= `INSN_VOP_INTR;
 194                                 else
 195                                         opcode <= busdata;
 196                                 rdata <= busdata;
 197                                 newcycle <= 0;
 198                                 cycle <= 0;
 199                         end else begin
 200                                 if (rd) rdata <= busdata;
 201                                 cycle <= cycle + 1;
 202                         end
 203                         if (iedelay) begin
 204                                 ie <= 1;
 205                                 iedelay <= 0;
 206                         end
 207                         buswr <= 0;
 208                         busrd <= 0;
 209                         wr <= 0;
 210                         rd <= 0;
 211                         address <= 16'bxxxxxxxxxxxxxxxx;        // Make it obvious if something of type has happened.
 212                         wdata <= 8'bxxxxxxxx;
 213                         state <= `STATE_EXECUTE;
 214                 end
 215                 `STATE_EXECUTE: begin
 216                         casex (opcode)
 217                         `define EXECUTE
 218                         `include "allinsns.v"
 219                         `undef EXECUTE
 220                         default:
 221                                 $stop;
 222                         endcase
 223                         state <= `STATE_WRITEBACK;
 224                 end
 225                 `STATE_WRITEBACK: begin
 226                         casex (opcode)
 227                         `define WRITEBACK
 228                         `include "allinsns.v"
 229                         `undef WRITEBACK
 230                         default:
 231                                 $stop;
 232                         endcase
 233                         state <= `STATE_FETCH;
 234                 end
 235                 endcase
 236 endmodule