Soundcore.v

   1 `define ADDR_NR50 16'hFF24
   2 `define ADDR_NR51 16'hFF25
   3 `define ADDR_NR52 16'hFF26
   4
   5 module Soundcore(
   6         input core_clk,
   7         input wr,
   8         input rd,
   9         input [15:0] addr,
  10         inout [7:0] data,
  11         output reg snd_data_l,
  12         output reg snd_data_r
  13         );
  14
  15         reg [7:0] nr50,nr51,nr52;
  16         reg [3:0] pwmcnt;
  17         reg [4:0] cntclk;
  18         reg [13:0] lenclk;
  19         wire [3:0] sndout1,sndout2,sndout3,sndout4;
  20         wire [3:0] right_snd = nr51[0] ? sndout1 : 4'b0;
  21         wire [3:0] left_snd = nr51[4] ? sndout1 : 4'b0;
  22
  23         assign sndout3 = 0;
  24         assign sndout4 = 0;
  25
  26         assign data = rd ?
  27                          addr == `ADDR_NR50 ? nr50 :
  28                          addr == `ADDR_NR51 ? nr51 :
  29                          addr == `ADDR_NR52 ? nr52 : 8'bzzzzzzzz
  30                       : 8'bzzzzzzzz;
  31
  32         always @ (negedge core_clk) begin
  33                 if(wr) begin
  34                         case(addr)
  35                         `ADDR_NR50: nr50 <= data;
  36                         `ADDR_NR51: nr51 <= data;
  37                         `ADDR_NR52: nr52 <= {data[7],3'b1,data[3:0]};
  38                         endcase
  39                 end
  40                 cntclk <= cntclk + 1;
  41                 lenclk <= lenclk + 1;
  42                 pwmcnt <= pwmcnt + 1;
  43                 snd_data_l <= (pwmcnt <= left_snd) ? 1 : 0;
  44                 snd_data_r <= (pwmcnt <= right_snd) ? 1 : 0;
  45         end
  46
  47         Sound1 s1(
  48                 .core_clk(core_clk),
  49                 .wr(wr),
  50                 .rd(rd),
  51                 .addr(addr),
  52                 .data(data),
  53                 .cntclk(cntclk[4]),
  54                 .lenclk(lenclk[13]),
  55                 .en(nr52[7] & nr52[0]),
  56                 .snd_data(sndout1)
  57         );
  58
  59         Sound2 s2(
  60                 .core_clk(core_clk),
  61                 .wr(wr),
  62                 .rd(rd),
  63                 .addr(addr),
  64                 .data(data),
  65                 .cntclk(cntclk[4]),
  66                 .lenclk(lenclk[13]),
  67                 .en(nr52[7] & nr52[0]),
  68                 .snd_data(sndout2)
  69         );
  70
  71 endmodule